Lines Matching +full:interrupt +full:- +full:affinity
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
30 interrupt-controller: true
32 "#address-cells":
34 "#size-cells":
39 "#interrupt-cells":
41 Specifies the number of cells needed to encode an interrupt source.
43 If the system requires describing PPI affinity, then the value must
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
50 The 2nd cell contains the interrupt number for the interrupt type.
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extented SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
61 interrupt is affine to. The interrupt must be a PPI, and the node
62 pointed must be a subnode of the "ppi-partitions" subnode. For
63 interrupt types other than PPI or PPIs that are not partitionned,
64 this cell must be zero. See the "ppi-partitions" node description
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
91 Interrupt source of the VGIC maintenance interrupt.
94 redistributor-stride:
102 "#redistributor-regions":
109 msi-controller:
111 Only present if the Message Based Interrupt functionnality is
112 being exposed by the HW, and the mbi-ranges property present.
114 mbi-ranges:
119 $ref: /schemas/types.yaml#/definitions/uint32-matrix
124 mbi-alias:
129 $ref: /schemas/types.yaml#/definitions/uint32-array
134 ppi-partitions:
137 PPI affinity can be expressed as a single "ppi-partitions" node,
138 containing a set of sub-nodes.
140 "^interrupt-partition-[0-9]+$":
143 affinity:
144 $ref: /schemas/types.yaml#/definitions/phandle-array
152 - affinity
157 clock-names:
159 - const: aclk
161 power-domains:
168 mbi-ranges: [ msi-controller ]
169 msi-controller: [ mbi-ranges ]
172 - compatible
173 - reg
176 "^gic-its@": false
177 "^interrupt-controller@[0-9a-f]+$": false
178 # msi-controller is preferred, but allow other names
179 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
182 GICv3 has one or more Interrupt Translation Services (ITS) that are
186 const: arm,gic-v3-its
188 msi-controller: true
190 "#msi-cells":
192 The single msi-cell is the DeviceID of the device which will generate
201 socionext,synquacer-pre-its:
204 address and size of the pre-ITS window.
205 $ref: /schemas/types.yaml#/definitions/uint32-array
211 - compatible
212 - msi-controller
213 - "#msi-cells"
214 - reg
221 - |
222 gic: interrupt-controller@2cf00000 {
223 compatible = "arm,gic-v3";
224 #interrupt-cells = <3>;
225 #address-cells = <1>;
226 #size-cells = <1>;
228 interrupt-controller;
236 msi-controller;
237 mbi-ranges = <256 128>;
239 msi-controller@2c200000 {
240 compatible = "arm,gic-v3-its";
241 msi-controller;
242 #msi-cells = <1>;
247 - |
248 interrupt-controller@2c010000 {
249 compatible = "arm,gic-v3";
250 #interrupt-cells = <4>;
251 #address-cells = <1>;
252 #size-cells = <1>;
254 interrupt-controller;
255 redistributor-stride = <0x0 0x40000>; // 256kB stride
256 #redistributor-regions = <2>;
258 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
259 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
265 msi-controller@2c200000 {
266 compatible = "arm,gic-v3-its";
267 msi-controller;
268 #msi-cells = <1>;
272 msi-controller@2c400000 {
273 compatible = "arm,gic-v3-its";
274 msi-controller;
275 #msi-cells = <1>;
279 ppi-partitions {
280 part0: interrupt-partition-0 {
281 affinity = <&cpu0>, <&cpu2>;
284 part1: interrupt-partition-1 {
285 affinity = <&cpu1>, <&cpu3>;