Lines Matching +full:bus +full:- +full:frequency
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
18 monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
23 The each AXI bus has the owned source clock but, has not the only owned power
24 line. The power line might be shared among one more sub-blocks. So, we can
25 divide into two type of device as the role of each sub-block. There are two
26 type of bus devices as following::
27 - parent bus device
28 - passive bus device
30 Basically, parent and passive bus device share the same power line. The
31 parent bus device can only change the voltage of shared power line and the
32 rest bus devices (passive bus device) depend on the decision of the parent
33 bus device. If there are three blocks which share the VDD_xxx power line,
37 VDD_xxx |--- A block (parent)
38 |--- B block (passive)
39 |--- C block (passive)
42 SoC has different sub-blocks. Therefore, such difference should be specified
44 able to support the bus frequency for all Exynos SoCs.
46 Detailed correlation between sub-blocks and power line according
48 - In case of Exynos3250, there are two power line as following::
49 VDD_MIF |--- DMC (Dynamic Memory Controller)
51 VDD_INT |--- LEFTBUS (parent device)
52 |--- PERIL
53 |--- MFC
54 |--- G3D
55 |--- RIGHTBUS
56 |--- PERIR
57 |--- FSYS
58 |--- LCD0
59 |--- PERIR
60 |--- ISP
61 |--- CAM
63 - MIF bus's frequency/voltage table
64 -----------------------
66 -----------------------
72 -----------------------
74 - INT bus's frequency/voltage table
75 ----------------------------------------------------------
80 ----------------------------------------------------------
82 ----------------------------------------------------------
83 |Lv |Frequency ||Voltage |
84 ----------------------------------------------------------
90 ----------------------------------------------------------
92 - In case of Exynos4210, there is one power line as following::
93 VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
94 |--- LEFTBUS
95 |--- PERIL
96 |--- MFC(L)
97 |--- G3D
98 |--- TV
99 |--- LCD0
100 |--- RIGHTBUS
101 |--- PERIR
102 |--- MFC(R)
103 |--- CAM
104 |--- FSYS
105 |--- GPS
106 |--- LCD0
107 |--- LCD1
109 - In case of Exynos4x12, there are two power line as following::
110 VDD_MIF |--- DMC (Dynamic Memory Controller)
112 VDD_INT |--- LEFTBUS (parent device)
113 |--- PERIL
114 |--- MFC(L)
115 |--- G3D
116 |--- TV
117 |--- IMAGE
118 |--- RIGHTBUS
119 |--- PERIR
120 |--- MFC(R)
121 |--- CAM
122 |--- FSYS
123 |--- GPS
124 |--- LCD0
125 |--- ISP
127 - In case of Exynos5422, there are two power line as following::
128 VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
129 |--- DREX 1
131 VDD_INT |--- NoC_Core (parent device)
132 |--- G2D
133 |--- G3D
134 |--- DISP1
135 |--- NoC_WCORE
136 |--- GSCL
137 |--- MSCL
138 |--- ISP
139 |--- MFC
140 |--- GEN
141 |--- PERIS
142 |--- PERIC
143 |--- FSYS
144 |--- FSYS2
146 - In case of Exynos5433, there is VDD_INT power line as following::
147 VDD_INT |--- G2D (parent device)
148 |--- MSCL
149 |--- GSCL
150 |--- JPEG
151 |--- MFC
152 |--- HEVC
153 |--- BUS0
154 |--- BUS1
155 |--- BUS2
156 |--- PERIS (Fixed clock rate)
157 |--- PERIC (Fixed clock rate)
158 |--- FSYS (Fixed clock rate)
163 - samsung,exynos-bus
168 clock-names:
170 - const: bus
175 Parent bus device. Valid and required only for the passive bus devices.
177 devfreq-events:
178 $ref: /schemas/types.yaml#/definitions/phandle-array
182 Devfreq-event device to monitor the current utilization of buses. Valid
183 and required only for the parent bus devices.
185 exynos,saturation-ratio:
189 total cycle count. Valid only for the parent bus devices.
191 '#interconnect-cells':
198 operating-points-v2: true
200 samsung,data-clock-ratio:
204 Ratio of the data throughput in B/s to minimum data clock frequency in
207 vdd-supply:
209 Main bus power rail. Valid and required only for the parent bus devices.
212 - compatible
213 - clocks
214 - clock-names
215 - operating-points-v2
220 - |
221 #include <dt-bindings/clock/exynos3250.h>
223 bus-dmc {
224 compatible = "samsung,exynos-bus";
226 clock-names = "bus";
227 operating-points-v2 = <&bus_dmc_opp_table>;
228 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
229 vdd-supply = <&buck1_reg>;
233 compatible = "samsung,exynos-ppmu";
236 ppmu_dmc0_3: ppmu-event3-dmc0 {
237 event-name = "ppmu-event3-dmc0";
242 bus_leftbus: bus-leftbus {
243 compatible = "samsung,exynos-bus";
245 clock-names = "bus";
246 operating-points-v2 = <&bus_leftbus_opp_table>;
247 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
248 vdd-supply = <&buck3_reg>;
251 bus-rightbus {
252 compatible = "samsung,exynos-bus";
254 clock-names = "bus";
255 operating-points-v2 = <&bus_leftbus_opp_table>;
259 - |
260 dmc: bus-dmc {
261 compatible = "samsung,exynos-bus";
263 clock-names = "bus";
264 operating-points-v2 = <&bus_dmc_opp_table>;
265 samsung,data-clock-ratio = <4>;
266 #interconnect-cells = <0>;
267 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
268 vdd-supply = <&buck1_reg>;
271 leftbus: bus-leftbus {
272 compatible = "samsung,exynos-bus";
274 clock-names = "bus";
275 operating-points-v2 = <&bus_leftbus_opp_table>;
277 #interconnect-cells = <0>;
278 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
279 vdd-supply = <&buck3_reg>;
282 display: bus-display {
283 compatible = "samsung,exynos-bus";
285 clock-names = "bus";
286 operating-points-v2 = <&bus_display_opp_table>;
288 #interconnect-cells = <0>;