Lines Matching full:exynos

4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
14   The Samsung Exynos SoC has many buses for data transfer between DRAM and
15   sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16   Generally, each bus of Exynos SoC includes a source clock and a power line,
22   The Exynos SoC includes the various sub-blocks which have the each AXI bus.
41   There are a little different composition among Exynos SoC because each Exynos
44   able to support the bus frequency for all Exynos SoCs.
47   to Exynos SoC::
163       - samsung,exynos-bus
185   exynos,saturation-ratio:
224         compatible = "samsung,exynos-bus";
233         compatible = "samsung,exynos-ppmu";
243         compatible = "samsung,exynos-bus";
252         compatible = "samsung,exynos-bus";
261         compatible = "samsung,exynos-bus";
272         compatible = "samsung,exynos-bus";
283         compatible = "samsung,exynos-bus";