Lines Matching +full:default +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
35 adi,channel-spacing:
40 adi,power-up-frequency:
45 adi,reference-div-factor:
48 If set the driver skips dynamic calculation and uses this default
51 adi,reference-doubler-enable:
55 adi,reference-div2-enable:
59 adi,phase-detector-polarity-positive-enable:
61 description: Enables positive phase detector polarity. Default negative.
63 adi,lock-detect-precision-6ns-enable:
65 description: Enables 6ns lock detect precision. Default = 10ns.
67 adi,lock-detect-function-integer-n-enable:
70 Enables lock detect for integer-N mode. Default = factional-N mode.
72 adi,charge-pump-current:
74 description: Charge pump current in mA. Default = 2500mA.
76 adi,muxout-select:
83 0: Three-State Output (default)
86 3: R-Counter output
87 4: N-Divider output
91 adi,low-spur-mode-enable:
93 description: Enables low spur mode. Default = Low noise mode.
95 adi,cycle-slip-reduction-enable:
99 adi,charge-cancellation-enable:
102 Enabled charge pump charge cancellation for integer-N modes.
104 adi,anti-backlash-3ns-enable:
107 Enables 3ns antibacklash pulse width for integer-N modes.
109 adi,band-select-clock-mode-high-enable:
113 adi,12bit-clk-divider:
116 Clock divider value used when adi,12bit-clkdiv-mode != 0
118 adi,clk-divider-mode:
122 Valid values for the clkdiv mode are:
123 0: Clock divider off (default)
127 adi,aux-output-enable:
131 adi,aux-output-fundamental-enable:
135 Default = Output of RF dividers.
137 adi,mute-till-lock-enable:
139 description: Enables Mute-Till-Lock-Detect function.
141 adi,output-power:
146 Valid values for the power mode are:
147 0: -4dBm (default)
148 1: -1dBm
152 adi,aux-output-power:
157 Valid values for the power mode are:
158 0: -4dBm (default)
159 1: -1dBm
166 - compatible
167 - reg
168 - clocks
171 - |
173 #address-cells = <1>;
174 #size-cells = <0>;
179 spi-max-frequency = <10000000>;
181 clock-names = "clkin";
182 adi,channel-spacing = <10000>;
183 adi,power-up-frequency = <2400000000>;
184 adi,phase-detector-polarity-positive-enable;
185 adi,charge-pump-current = <2500>;
186 adi,output-power = <3>;
187 adi,mute-till-lock-enable;