Lines Matching +full:single +full:- +full:ended
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 STM32 ADC is a successive approximation analog-to-digital converter.
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
29 - st,stm32mp1-adc-core
37 - stm32f4 and stm32h7 share a common ADC interrupt line.
38 - stm32mp1 has two separate interrupt lines, one for each ADC within
48 - "adc" clock: for the analog circuitry, common to all ADCs.
51 - "bus" clock: for registers access, common to all ADCs.
55 clock-names: true
57 st,max-clk-rate-hz:
61 vdda-supply:
64 vref-supply:
67 booster-supply:
72 vdd-supply:
81 $ref: "/schemas/types.yaml#/definitions/phandle-array"
83 interrupt-controller: true
85 '#interrupt-cells':
88 '#address-cells':
91 '#size-cells':
95 - if:
99 const: st,stm32f4-adc-core
106 clock-names:
111 - description: interrupt line common for all ADCs
113 st,max-clk-rate-hz:
118 booster-supply: false
120 vdd-supply: false
124 - if:
128 const: st,stm32h7-adc-core
136 clock-names:
138 - const: bus
139 - const: adc
144 - description: interrupt line common for all ADCs
146 st,max-clk-rate-hz:
151 vdd-supply: false
155 - if:
159 const: st,stm32mp1-adc-core
167 clock-names:
169 - const: bus
170 - const: adc
175 - description: interrupt line for ADC1
176 - description: interrupt line for ADC2
178 st,max-clk-rate-hz:
186 - compatible
187 - reg
188 - interrupts
189 - clocks
190 - clock-names
191 - vdda-supply
192 - vref-supply
193 - interrupt-controller
194 - '#interrupt-cells'
195 - '#address-cells'
196 - '#size-cells'
199 "^adc@[0-9]+$":
208 - st,stm32f4-adc
209 - st,stm32h7-adc
210 - st,stm32mp1-adc
215 - 0x0: ADC1
216 - 0x100: ADC2
217 - 0x200: ADC3 (stm32f4 only)
220 '#io-channel-cells':
223 '#address-cells':
226 '#size-cells':
232 - 0 for adc@0
233 - 1 for adc@100
234 - 2 for adc@200 (stm32f4 only)
247 dma-names:
250 assigned-resolution-bits:
253 - can be 6, 8, 10 or 12 on stm32f4
254 - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
256 st,adc-channels:
258 List of single-ended channels muxed for this ADC. It can have up to:
259 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
260 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
262 $ref: /schemas/types.yaml#/definitions/uint32-array
265 st,adc-diff-channels:
268 be configured as differential instead of single-ended on stm32h7 and
272 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
276 used as single-ended and some other ones as differential (mixed). But
277 channels can't be configured both as single-ended and differential.
278 $ref: /schemas/types.yaml#/definitions/uint32-matrix
281 - description: |
285 - description: |
291 st,min-sample-time-nsecs:
296 array that matches "st,adc-channels" and/or "st,adc-diff-channels"
299 $ref: /schemas/types.yaml#/definitions/uint32-array
302 nvmem-cells:
304 - description: Phandle to the calibration vrefint data provided by otp
306 nvmem-cell-names:
308 - const: vrefint
311 "^channel@([0-9]|1[0-9])$":
328 diff-channels:
329 $ref: /schemas/types.yaml#/definitions/uint32-array
334 st,min-sample-time-ns:
341 - reg
346 - if:
350 const: st,stm32f4-adc
356 - 0x0
357 - 0x100
358 - 0x200
364 assigned-resolution-bits:
368 st,adc-channels:
375 st,adc-diff-channels: false
377 st,min-sample-time-nsecs:
384 - clocks
386 - if:
391 - st,stm32h7-adc
392 - st,stm32mp1-adc
398 - 0x0
399 - 0x100
405 assigned-resolution-bits:
409 st,adc-channels:
416 st,min-sample-time-nsecs:
425 - compatible
426 - reg
427 - interrupts
428 - '#io-channel-cells'
431 - |
432 // Example 1: with stm32f429, ADC1, single-ended channel 8
434 compatible = "st,stm32f4-adc-core";
438 clock-names = "adc";
439 st,max-clk-rate-hz = <36000000>;
440 vdda-supply = <&vdda>;
441 vref-supply = <&vref>;
442 interrupt-controller;
443 #interrupt-cells = <1>;
444 #address-cells = <1>;
445 #size-cells = <0>;
447 compatible = "st,stm32f4-adc";
448 #io-channel-cells = <1>;
451 interrupt-parent = <&adc123>;
453 st,adc-channels = <8>;
455 dma-names = "rx";
456 assigned-resolution-bits = <8>;
462 - |
464 // - channels 0 & 1 as single-ended
465 // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
466 #include <dt-bindings/interrupt-controller/arm-gic.h>
467 #include <dt-bindings/clock/stm32mp1-clks.h>
469 compatible = "st,stm32mp1-adc-core";
474 clock-names = "bus", "adc";
475 booster-supply = <&booster>;
476 vdd-supply = <&vdd>;
477 vdda-supply = <&vdda>;
478 vref-supply = <&vref>;
480 interrupt-controller;
481 #interrupt-cells = <1>;
482 #address-cells = <1>;
483 #size-cells = <0>;
485 compatible = "st,stm32mp1-adc";
486 #io-channel-cells = <1>;
488 interrupt-parent = <&adc12>;
490 st,adc-channels = <0 1>;
491 st,adc-diff-channels = <2 6>, <3 7>;
492 st,min-sample-time-nsecs = <5000>;
494 dma-names = "rx";
500 - |
502 // - internal channels 13, 14, 15.
503 #include <dt-bindings/interrupt-controller/arm-gic.h>
504 #include <dt-bindings/clock/stm32mp1-clks.h>
506 compatible = "st,stm32mp1-adc-core";
511 clock-names = "bus", "adc";
512 booster-supply = <&booster>;
513 vdd-supply = <&vdd>;
514 vdda-supply = <&vdda>;
515 vref-supply = <&vref>;
517 interrupt-controller;
518 #interrupt-cells = <1>;
519 #address-cells = <1>;
520 #size-cells = <0>;
522 compatible = "st,stm32mp1-adc";
523 #io-channel-cells = <1>;
526 #address-cells = <1>;
527 #size-cells = <0>;
531 st,min-sample-time-ns = <9000>;
536 st,min-sample-time-ns = <9000>;
541 st,min-sample-time-ns = <9000>;