Lines Matching full:each
37 aliases" in address space, each of which access the same underlying
42 implemented by the SoC. Each GPIO is assigned to a port, and a port may
43 control a number of GPIOs. Thus, each GPIO is named according to an
47 The number of ports implemented by each GPIO controller varies. The number
48 of implemented GPIOs within each port varies. GPIO registers within a
60 Each GPIO controller can generate a number of interrupt signals. Each
67 Each GPIO controller in fact generates multiple interrupts signals for
68 each set of ports. Each GPIO may be configured to feed into a specific
70 for each generated signal to be routed to a different CPU, thus allowing
71 different CPUs to each handle subsets of the interrupts within a port.
72 The status of each of these per-port-set signals is reported via a