Lines Matching +full:in +full:- +full:gpios
4 1) gpios property
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
9 for compatibility reasons (resolving to the "gpios" property), it is not allowed
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
15 cases should they contain more than one. If your device uses several GPIOs with
17 meaningful name. The only case where an array of GPIOs is accepted is when
18 several GPIOs serve the same function (e.g. a parallel data line).
20 The exact purpose of each gpios property must be documented in the device tree
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
37 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
43 documented in the device tree binding for the device, but it is strongly
44 recommended to use the two-cell approach.
46 Most controllers are specifying a generic flag bitfield in the last cell, so
47 for these, use the macros defined in
48 include/dt-bindings/gpio/gpio.h whenever possible:
50 Example of a node using GPIOs:
53 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
56 GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
57 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
61 - Bit 0: 0 means active high, 1 means active low
62 - Bit 1: 0 mean push-pull wiring, see:
63 https://en.wikipedia.org/wiki/Push-pull_output
64 1 means single-ended wiring, see:
65 https://en.wikipedia.org/wiki/Single-ended_triode
66 - Bit 2: 0 means open-source, 1 means open drain, see:
68 - Bit 3: 0 means the output should be maintained during sleep/low-power mode
69 1 means the output state can be lost during sleep/low-power mode
70 - Bit 4: 0 means no pull-up resistor should be enabled
71 1 means a pull-up resistor should be enabled
73 control for pull-up configuration. If the hardware has more
74 elaborate pull-up configuration, it should be represented
76 - Bit 5: 0 means no pull-down resistor should be enabled
77 1 means a pull-down resistor should be enabled
79 control for pull-down configuration. If the hardware has more
80 elaborate pull-down configuration, it should be represented
84 ----------------------------------
86 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
87 high or active-low. If it does, the following best practices should be
90 The gpio-specifier's polarity flag should represent the physical level at the
94 the GPIO controller and the device, then the gpio-specifier will represent the
106 a1) (Preferred) Dictated by a binding-specific DT property.
112 In particular, the polarity cannot be derived from the gpio-specifier, since
114 concepts of configurable signal polarity in the device, and possible board-
120 in the binding. The gpio-specifier should represent the polarity of the signal
127 2) gpio-controller nodes
128 ------------------------
130 Every GPIO controller node must contain both an empty "gpio-controller"
131 property, and a #gpio-cells integer property, which indicates the number of
132 cells in a gpio-specifier.
134 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
137 exposed in the device tree as an individual gpio-controller node, reflecting
142 indicates the number of in-use slots of available slots for GPIOs. The
146 in a lot of designs, some using all 32 bits, some using 18 and some using
147 12. In this case, setting "ngpios = <18>;" informs the driver that only the
148 first 18 GPIOs, at local offset 0 .. 17, are in use.
150 If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
151 additional set of tuples is needed to specify which GPIOs are unusable, with
152 the gpio-reserved-ranges binding. This property indicates the start and size
153 of the GPIOs that can't be used.
155 Optionally, a GPIO controller may have a "gpio-line-names" property. This is
161 helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
165 in your design. The names are assigned starting from line offset 0 from
172 gpio-controller@00000000 {
175 gpio-controller;
176 #gpio-cells = <2>;
178 gpio-reserved-ranges = <0 4>, <12 2>;
179 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
187 gpio-controller's driver probe function.
191 - gpio-hog: A property specifying that this child node represents a GPIO hog.
192 - gpios: Store the GPIO information (id, flags, ...) for each GPIO to
194 specified in its parent node (GPIO controller node).
195 Only one of the following properties scanned in the order shown below.
197 in the order presented below and the first match is taken as the intended
199 - input: A property specifying to set the GPIO direction as input.
200 - output-low A property specifying to set the GPIO direction as output with
202 - output-high A property specifying to set the GPIO direction as output with
206 - line-name: The GPIO label name. If not present the node name is used.
208 Example of two SOC GPIO banks defined as gpio-controller nodes:
210 qe_pio_a: gpio-controller@1400 {
211 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
213 gpio-controller;
214 #gpio-cells = <2>;
216 line_b-hog {
217 gpio-hog;
218 gpios = <6 0>;
219 output-low;
220 line-name = "foo-bar-gpio";
224 qe_pio_e: gpio-controller@1460 {
225 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
227 gpio-controller;
228 #gpio-cells = <2>;
231 2.1) gpio- and pin-controller interaction
232 -----------------------------------------
234 Some or all of the GPIOs provided by a GPIO controller may be routed to pins
240 -------------------------------------
242 It is useful to represent which GPIOs correspond to which pins on which pin
243 controllers. The gpio-ranges property described below represents this with
245 to pins in the GPIO controller local number space.
254 described in pinctrl/pinctrl-bindings.txt.
257 ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but
258 in practice these ranges are often lumped in discrete sets.
262 gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;
265 - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and
266 - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29
271 qe_pio_e: gpio-controller@1460 {
272 #gpio-cells = <2>;
273 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
275 gpio-controller;
276 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
279 Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
280 pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
285 --------------------------------------
290 Both both <pinctrl-base> and <count> must set to 0 when using named pin groups
293 The property gpio-ranges-group-names must contain exactly one string for each
296 Elements of gpio-ranges-group-names must contain the name of a pin group
297 defined in the respective pin controller. The number of pins/GPIO lines in the
298 range is the number of pins in that pin group. The number of pins of that
299 group is defined int the implementation and not in the device tree.
302 numerical pin range in gpio-ranges-group-names must be empty.
306 gpio_pio_i: gpio-controller@14b0 {
307 #gpio-cells = <2>;
308 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
310 gpio-controller;
311 gpio-ranges = <&pinctrl1 0 20 10>,
315 gpio-ranges-group-names = "",
324 in pinctrl2 are defined using the pin groups named "foo" and "bar".
327 were referenced by any gpio-ranges property to contain a property named
328 #gpio-range-cells with value <3>. This requirement is now deprecated.
329 However, that property may still exist in older device trees for
330 compatibility reasons, and would still be required even in new device