Lines Matching full:region

1 FPGA Region Device Tree Binding
9  - FPGA Region
39 Partial Reconfiguration Region (PRR)
46    into a PRR must fit and must use a subset of the region's connections.
47  * The busses within the FPGA are split such that each region gets its own
64  * During Partial Reconfiguration of a specific region, that region's bridge
100 region (PRR0-2) gets its own split of the busses that is independently gated by
108 When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
117 When the overlay is removed, the child nodes will be removed and the FPGA Region
121 FPGA Region
125 Region brings together the elements needed to program on a running system and
136 An FPGA Region that exists in the live Device Tree reflects the current state.
138 Region, the FPGA already has been programmed.  A DTO that targets an FPGA Region
143 The base FPGA Region in the device tree represents the FPGA and supports full
145 FPGA region will be the child of one of the hardware bridges (the bridge that
147 one bridge to control during FPGA programming, the region will also contain a
150 For partial reconfiguration (PR), each PR region will have an FPGA Region.
152 base FPGA region.  The "Full Reconfiguration to add PRR's" example below shows
155 If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
156 Manager specified by its ancestor FPGA Region.  This supports both the case
158 a different FPGA Manager is used for each region.
162 region is getting reconfigured (see Figure 1 above).  During PR, the FPGA's
167 - compatible : should contain "fpga-region"
170 	in a region will override any inherited FPGA manager.
178 	If this property is in an overlay targeting an FPGA region, it is a
183         If the fpga-region is  the child of an fpga-bridge, the list should not
190 - region-unfreeze-timeout-us : The maximum time in microseconds to wait for
191 	bridges to successfully become enabled after the region has been
193 - region-freeze-timeout-us : The maximum time in microseconds to wait for
194 	bridges to successfully become disabled before the region has been
197 	FPGA to go to operating mode after the region has been programmed.
202 programming: the parent fpga_bridge0 and fpga_bridge1.  Because the region is
206 specified in the region.  If FPGA programming succeeds, the bridges are
210 bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
234 			compatible = "fpga-region";
281 a FPGA Region.  The target of the Device Tree Overlay is the FPGA Region.  Some
293    FPGA Region.  The FPGA Region is the child of the bridge that allows
295    fpga-bridges property in the FPGA region or in the device tree overlay.
301    region while the buses are enabled for other sections.  Before any partial
303    PRR's with FPGA bridges.  The device tree should have an FPGA region for each
313  * FPGA Region
322 The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA
323 Bridges.  The FPGA Region's "fpga-mgr" property specifies the manager by phandle
324 to handle programming the FPGA.  If the FPGA Region is the child of another FPGA
325 Region, the parent's FPGA Manager is used.  If FPGA Bridges need to be involved,
326 they are specified in the FPGA Region by the "fpga-bridges" property.  During
327 FPGA programming, the FPGA Region will disable the bridges that are in its
343  * child nodes corresponding to hardware that will be loaded in this region of
361 		compatible = "fpga-region";
391 The base FPGA Region is specified similar to the first example above.
394 configured.  Each region has its own bridge in the FPGA fabric.
412 			compatible = "fpga-region";
424 			compatible = "fpga-region";
470 or region it is designed to go into.