Lines Matching full:bridges

58  * FPGA Bridges gate bus signals between a host and FPGA.
59  * FPGA Bridges should be disabled while the FPGA is being programmed to
61  * FPGA bridges may be actual hardware or soft logic on an FPGA.
62  * During Full Reconfiguration, hardware bridges between the host and FPGA
67    buses, eliminating the need to show the hardware FPGA bridges in the
111  1. Disable appropriate FPGA bridges.
113  3. Enable the FPGA bridges.
118 will disable the bridges.
129  * FPGA Bridges
145 FPGA region will be the child of one of the hardware bridges (the bridge that
148 list of phandles to the additional hardware FPGA Bridges.
151 These FPGA regions are children of FPGA bridges which are then children of the
160 FPGA Regions do not inherit their ancestor FPGA regions' bridges.  This prevents
161 shutting down bridges that are upstream from the other active regions while one
163 hardware bridges remain enabled.  The PR regions' bridges will be FPGA bridges
180 - fpga-bridges : should contain a list of phandles to FPGA Bridges that must be
182 	This property is optional if the FPGA Manager handles the bridges.
191 	bridges to successfully become enabled after the region has been
194 	bridges to successfully become disabled before the region has been
201 fpga_mgr is used to program the FPGA.  Two bridges are controlled during
204 fpga-bridges property.  During programming, these bridges are disabled, the
206 specified in the region.  If FPGA programming succeeds, the bridges are
208 are then populated.  If FPGA programming fails, the bridges are left disabled
256 	fpga-bridges = <&fpga_bridge1>;
280 In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
284  * No FPGA Bridges
286    bridges behind the scenes.  No FPGA Bridge devices are needed for full
289  * Full reconfiguration with hardware bridges
290    In this case, there are hardware bridges between the processor and FPGA that
292    applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
294    register access to the FPGA.  Additional bridges may be listed in a
295    fpga-bridges property in the FPGA region or in the device tree overlay.
297  * Partial reconfiguration with bridges in the FPGA
300    bridges need to exist in the FPGA that can gate the buses going to each FPGA
303    PRR's with FPGA bridges.  The device tree should have an FPGA region for each
312  * FPGA Bridges
323 Bridges.  The FPGA Region's "fpga-mgr" property specifies the manager by phandle
325 Region, the parent's FPGA Manager is used.  If FPGA Bridges need to be involved,
326 they are specified in the FPGA Region by the "fpga-bridges" property.  During
327 FPGA programming, the FPGA Region will disable the bridges that are in its
328 "fpga-bridges" list and will re-enable them after FPGA programming has
346 Device Tree Example: Full Reconfiguration without Bridges
474 FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.