Lines Matching +full:zynqmp +full:- +full:aes

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Nava kishore Manne <nava.manne@xilinx.com>
12 description: The zynqmp-firmware node describes the interface to platform
13   firmware. ZynqMP has an interface to communicate with secure firmware.
23       - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24         const: xlnx,zynqmp-firmware
26       - description: For implementations complying for Versal.
27         const: xlnx,versal-firmware
31                  The method of calling the PM-API firmware layer.
33                  - "smc" : SMC #0, following the SMCCC
34                  - "hvc" : HVC #0, following the SMCCC
36     $ref: /schemas/types.yaml#/definitions/string-array
38       - smc
39       - hvc
42     $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
46   zynqmp-aes:
47     $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
48     description: The ZynqMP AES-GCM hardened cryptographic accelerator is
53   clock-controller:
54     $ref: /schemas/clock/xlnx,versal-clk.yaml#
63   - compatible
68   - |
69     versal-firmware {
70       compatible = "xlnx,versal-firmware";
74         compatible = "xlnx,versal-fpga";
77       xlnx_aes: zynqmp-aes {
78         compatible = "xlnx,zynqmp-aes";
81       versal_clk: clock-controller {
82         #clock-cells = <1>;
83         compatible = "xlnx,versal-clk";
85         clock-names = "ref", "alt_ref", "pl_alt_ref";