Lines Matching +full:per +full:- +full:channel

2 It can be configured to have one channel or two channels. If configured
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 		"xlnx,axi-vdma-1.00.a"
21 		"xlnx,axi-dma-1.00.a"
22 		"xlnx,axi-cdma-1.00.a"
23 		"xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
25 - reg: Should contain VDMA registers location and length.
26 - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
27 - dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
28 - dma-channel child node: Should have at least one channel and can have up to
29 	two channels per device. This node specifies the properties of each
30 	DMA channel (see child node properties below).
31 - clocks: Input clock specifier. Refer to common clock bindings.
32 - clock-names: List of input clocks
45 - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
48 - xlnx,sg-length-width: Should be set to the width in bits of the length
53 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
56 	{2}, flush mm2s channel
57 	{3}, flush s2mm channel
60 - compatible:
61 	For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
62 	"xlnx,axi-vdma-s2mm-channel".
63 	For CDMA: It should be "xlnx,axi-cdma-channel".
64 	For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"
65 	or "xlnx,axi-dma-s2mm-channel".
66 - interrupts: Should contain per channel VDMA interrupts.
67 - xlnx,datawidth: Should contain the stream data width, take values
71 - xlnx,include-dre: Tells hardware is configured for Data
74 - xlnx,genlock-mode: Tells Genlock synchronization is
76 - xlnx,enable-vert-flip: Tells vertical flip is
79 - dma-channels: Number of dma channels in child node.
85 	compatible = "xlnx,axi-vdma-1.00.a";
88 	dma-ranges = <0x00000000 0x00000000 0x40000000>;
89 	xlnx,num-fstores = <0x8>;
90 	xlnx,flush-fsync = <0x1>;
93 	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
95 	dma-channel@40030000 {
96 		compatible = "xlnx,axi-vdma-mm2s-channel";
100 	dma-channel@40030030 {
101 		compatible = "xlnx,axi-vdma-s2mm-channel";
111 - dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
112 	where Channel ID is '0' for write/tx and '1' for read/rx
113 	channel. For MCMDA, MM2S channel(write/tx) ID start from
114 	'0' and is in [0-15] range. S2MM channel(read/rx) ID start
115 	from '16' and is in [16-31] range. These channels ID are
118 - dma-names: a list of DMA channel names, one per "dmas" entry
124 	compatible ="xlnx,axi-vdma-test-1.00.a";
127 	dma-names = "vdma0", "vdma1";