Lines Matching +full:sci +full:- +full:dev +full:- +full:id
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
15 The UDMA-P is intended to perform similar (but significantly upgraded)
16 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
18 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
29 on the Rx PSI-L interface.
31 The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
32 channels. Channels in the UDMA-P can be configured to be either Packet-Based
33 or Third-Party channels on a channel by channel basis.
35 All transfers within NAVSS is done between PSI-L source and destination
37 The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
38 legacy, non PSI-L native peripherals. In the later case a special, small PDMA
39 is tasked to act as a bridge between the PSI-L fabric and the legacy
46 - $ref: "../dma-controller.yaml#"
49 "#dma-cells":
53 The cell is the PSI-L thread ID of the remote (to UDMAP) end.
54 Valid ranges for thread ID depends on the data movement direction:
55 for source thread IDs (rx): 0 - 0x7fff
56 for destination thread IDs (tx): 0x8000 - 0xffff
58 Please refer to the device documentation for the PSI-L thread map and also
59 the PSI-L peripheral chapter for the correct thread ID.
61 When #dma-cells is 2, the second parameter is the channel ATYPE.
65 - ti,am654-navss-main-udmap
66 - ti,am654-navss-mcu-udmap
67 - ti,j721e-navss-main-udmap
68 - ti,j721e-navss-mcu-udmap
73 reg-names:
75 - const: gcfg
76 - const: rchanrt
77 - const: tchanrt
79 msi-parent: true
81 ti,sci:
82 description: phandle to TI-SCI compatible System controller node
85 ti,sci-dev-id:
86 description: TI-SCI device id of UDMAP
93 ti,sci-rm-range-tchan:
97 $ref: /schemas/types.yaml#/definitions/uint32-array
102 ti,sci-rm-range-rchan:
106 $ref: /schemas/types.yaml#/definitions/uint32-array
111 ti,sci-rm-range-rflow:
115 $ref: /schemas/types.yaml#/definitions/uint32-array
121 - compatible
122 - "#dma-cells"
123 - reg
124 - reg-names
125 - msi-parent
126 - ti,sci
127 - ti,sci-dev-id
128 - ti,ringacc
129 - ti,sci-rm-range-tchan
130 - ti,sci-rm-range-rchan
131 - ti,sci-rm-range-rflow
135 "#dma-cells":
139 ti,udma-atype:
144 - ti,udma-atype
149 - |+
151 #address-cells = <2>;
152 #size-cells = <2>;
155 compatible = "simple-mfd";
156 #address-cells = <2>;
157 #size-cells = <2>;
158 dma-coherent;
159 dma-ranges;
162 ti,sci-dev-id = <118>;
164 main_udmap: dma-controller@31150000 {
165 compatible = "ti,am654-navss-main-udmap";
169 reg-names = "gcfg", "rchanrt", "tchanrt";
170 #dma-cells = <1>;
174 msi-parent = <&inta_main_udmass>;
176 ti,sci = <&dmsc>;
177 ti,sci-dev-id = <188>;
179 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
181 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
183 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */