Lines Matching +full:tegra186 +full:- +full:bpmp

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Hub
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
22 '#address-cells':
25 '#size-cells':
38 clock-names:
44 - description: display hub reset
45 - description: window group 0 reset
46 - description: window group 1 reset
47 - description: window group 2 reset
48 - description: window group 3 reset
49 - description: window group 4 reset
50 - description: window group 5 reset
52 reset-names:
54 - const: misc
55 - const: wgrp0
56 - const: wgrp1
57 - const: wgrp2
58 - const: wgrp3
59 - const: wgrp4
60 - const: wgrp5
62 power-domains:
69 "^display@[0-9a-f]+$":
73 - if:
77 const: nvidia,tegra186-display
82 - description: display core clock
83 - description: display stream compression clock
84 - description: display hub clock
86 clock-names:
88 - const: disp
89 - const: dsc
90 - const: hub
95 - description: display core clock
96 - description: display hub clock
98 clock-names:
100 - const: disp
101 - const: hub
106 - compatible
107 - reg
108 - clocks
109 - clock-names
110 - resets
111 - reset-names
112 - power-domains
113 - "#address-cells"
114 - "#size-cells"
115 - ranges
118 - |
119 #include <dt-bindings/clock/tegra186-clock.h>
120 #include <dt-bindings/interrupt-controller/arm-gic.h>
121 #include <dt-bindings/memory/tegra186-mc.h>
122 #include <dt-bindings/power/tegra186-powergate.h>
123 #include <dt-bindings/reset/tegra186-reset.h>
125 display-hub@15200000 {
126 compatible = "nvidia,tegra186-display";
128 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
129 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
130 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
131 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
132 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
133 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
134 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
135 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
137 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
138 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
139 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
140 clock-names = "disp", "dsc", "hub";
143 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
145 #address-cells = <1>;
146 #size-cells = <1>;
151 compatible = "nvidia,tegra186-dc";
154 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
155 clock-names = "dc";
156 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
157 reset-names = "dc";
159 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
162 interconnect-names = "dma-mem", "read-1";
170 compatible = "nvidia,tegra186-dc";
173 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
174 clock-names = "dc";
175 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
176 reset-names = "dc";
178 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
181 interconnect-names = "dma-mem", "read-1";
189 compatible = "nvidia,tegra186-dc";
192 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
193 clock-names = "dc";
194 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
195 reset-names = "dc";
197 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
200 interconnect-names = "dma-mem", "read-1";
208 - |
209 #include <dt-bindings/clock/tegra194-clock.h>
210 #include <dt-bindings/interrupt-controller/arm-gic.h>
211 #include <dt-bindings/memory/tegra194-mc.h>
212 #include <dt-bindings/power/tegra194-powergate.h>
213 #include <dt-bindings/reset/tegra194-reset.h>
215 display-hub@15200000 {
216 compatible = "nvidia,tegra194-display";
218 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
219 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
220 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
221 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
222 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
223 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
224 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
225 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
227 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
228 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
229 clock-names = "disp", "hub";
232 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
234 #address-cells = <1>;
235 #size-cells = <1>;
240 compatible = "nvidia,tegra194-dc";
243 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
244 clock-names = "dc";
245 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
246 reset-names = "dc";
248 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
251 interconnect-names = "dma-mem", "read-1";
258 compatible = "nvidia,tegra194-dc";
261 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
262 clock-names = "dc";
263 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
264 reset-names = "dc";
266 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
269 interconnect-names = "dma-mem", "read-1";
276 compatible = "nvidia,tegra194-dc";
279 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
280 clock-names = "dc";
281 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
282 reset-names = "dc";
284 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
287 interconnect-names = "dma-mem", "read-1";
294 compatible = "nvidia,tegra194-dc";
297 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
298 clock-names = "dc";
299 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
300 reset-names = "dc";
302 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
305 interconnect-names = "dma-mem", "read-1";