Lines Matching +full:dt +full:- +full:compatible
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Rob Clark <robdclark@gmail.com>
14 compatible:
16 - description: |
18 figure out the gpu-id and patch level.
20 - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
21 - const: qcom,adreno
22 - description: |
24 figure out the gpu-id and patch level.
26 - pattern: '^amd,imageon-200\.[0-1]$'
27 - const: amd,imageon
31 clock-names: true
37 reg-names:
40 - const: kgsl_3d0_reg_memory
41 - const: cx_mem
42 - const: cx_dbgc
47 interrupt-names:
54 interconnect-names:
57 - const: gfx-mem
58 - const: ocmem
65 $ref: /schemas/types.yaml#/definitions/phandle-array
71 phandles to one or more reserved on-chip SRAM regions.
76 operating-points-v2: true
77 opp-table:
80 power-domains:
83 zap-shader:
87 For a5xx and a6xx devices this node contains a memory-region that
91 memory-region:
94 firmware-name:
98 "#cooling-cells":
101 nvmem-cell-names:
104 nvmem-cells:
116 - compatible
117 - reg
118 - interrupts
123 - if:
125 compatible:
127 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
135 clock-names:
138 - const: core
140 - const: iface
142 - const: mem
144 - const: mem_iface
146 - const: alt_mem_iface
148 - const: gfx3d
150 - const: rbbmtimer
156 - clocks
157 - clock-names
158 - if:
160 compatible:
162 pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
167 clock-names: false
170 - |
174 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
175 #include <dt-bindings/clock/qcom,rpmcc.h>
176 #include <dt-bindings/interrupt-controller/irq.h>
177 #include <dt-bindings/interrupt-controller/arm-gic.h>
180 compatible = "qcom,adreno-330.2", "qcom,adreno";
183 reg-names = "kgsl_3d0_reg_memory";
185 clock-names = "core", "iface", "mem_iface";
191 interrupt-names = "kgsl_3d0_irq";
194 power-domains = <&mmcc OXILICX_GDSC>;
195 operating-points-v2 = <&gpu_opp_table>;
197 #cooling-cells = <2>;
201 compatible = "qcom,msm8974-ocmem";
205 reg-names = "ctrl", "mem";
209 clock-names = "core", "iface";
211 #address-cells = <1>;
212 #size-cells = <1>;
215 gpu_sram: gpu-sram@0 {
219 - |
223 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
224 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
225 #include <dt-bindings/power/qcom-rpmpd.h>
226 #include <dt-bindings/interrupt-controller/irq.h>
227 #include <dt-bindings/interrupt-controller/arm-gic.h>
228 #include <dt-bindings/interconnect/qcom,sdm845.h>
230 reserved-memory {
231 #address-cells = <2>;
232 #size-cells = <2>;
235 compatible = "shared-dma-pool";
237 no-map;
242 compatible = "qcom,adreno-630.2", "qcom,adreno";
245 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
247 #cooling-cells = <2>;
253 operating-points-v2 = <&gpu_opp_table>;
256 interconnect-names = "gfx-mem";
260 gpu_opp_table: opp-table {
261 compatible = "operating-points-v2";
263 opp-430000000 {
264 opp-hz = /bits/ 64 <430000000>;
265 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
266 opp-peak-kBps = <5412000>;
269 opp-355000000 {
270 opp-hz = /bits/ 64 <355000000>;
271 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
272 opp-peak-kBps = <3072000>;
275 opp-267000000 {
276 opp-hz = /bits/ 64 <267000000>;
277 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
278 opp-peak-kBps = <3072000>;
281 opp-180000000 {
282 opp-hz = /bits/ 64 <180000000>;
283 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
284 opp-peak-kBps = <1804000>;
288 zap-shader {
289 memory-region = <&zap_shader_region>;
290 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";