Lines Matching +full:display +full:- +full:hub
1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
6 $id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
7 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
12 - Rob Clark <robdclark@gmail.com>
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
24 - const: qcom,adreno-gmu
30 reg-names:
38 clock-names:
44 - description: GMU HFI interrupt
45 - description: GMU interrupt
48 interrupt-names:
50 - const: hfi
51 - const: gmu
53 power-domains:
55 - description: CX power domain
56 - description: GX power domain
58 power-domain-names:
60 - const: cx
61 - const: gx
66 operating-points-v2: true
68 opp-table:
72 - compatible
73 - reg
74 - reg-names
75 - clocks
76 - clock-names
77 - interrupts
78 - interrupt-names
79 - power-domains
80 - power-domain-names
81 - iommus
82 - operating-points-v2
87 - if:
92 - qcom,adreno-gmu-618.0
93 - qcom,adreno-gmu-630.2
98 - description: Core GMU registers
99 - description: GMU PDC registers
100 - description: GMU PDC sequence registers
101 reg-names:
103 - const: gmu
104 - const: gmu_pdc
105 - const: gmu_pdc_seq
108 - description: GMU clock
109 - description: GPU CX clock
110 - description: GPU AXI clock
111 - description: GPU MEMNOC clock
112 clock-names:
114 - const: gmu
115 - const: cxo
116 - const: axi
117 - const: memnoc
119 - if:
124 - qcom,adreno-gmu-635.0
129 - description: Core GMU registers
130 - description: Resource controller registers
131 - description: GMU PDC registers
132 reg-names:
134 - const: gmu
135 - const: rscc
136 - const: gmu_pdc
139 - description: GMU clock
140 - description: GPU CX clock
141 - description: GPU AXI clock
142 - description: GPU MEMNOC clock
143 - description: GPU AHB clock
144 - description: GPU HUB CX clock
145 - description: GPU SMMU vote clock
146 clock-names:
148 - const: gmu
149 - const: cxo
150 - const: axi
151 - const: memnoc
152 - const: ahb
153 - const: hub
154 - const: smmu_vote
156 - if:
161 - qcom,adreno-gmu-640.1
166 - description: Core GMU registers
167 - description: GMU PDC registers
168 - description: GMU PDC sequence registers
169 reg-names:
171 - const: gmu
172 - const: gmu_pdc
173 - const: gmu_pdc_seq
175 - if:
180 - qcom,adreno-gmu-650.2
185 - description: Core GMU registers
186 - description: Resource controller registers
187 - description: GMU PDC registers
188 - description: GMU PDC sequence registers
189 reg-names:
191 - const: gmu
192 - const: rscc
193 - const: gmu_pdc
194 - const: gmu_pdc_seq
196 - if:
201 - qcom,adreno-gmu-640.1
202 - qcom,adreno-gmu-650.2
207 - description: GPU AHB clock
208 - description: GMU clock
209 - description: GPU CX clock
210 - description: GPU AXI clock
211 - description: GPU MEMNOC clock
212 clock-names:
214 - const: ahb
215 - const: gmu
216 - const: cxo
217 - const: axi
218 - const: memnoc
221 - |
222 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
223 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
224 #include <dt-bindings/interrupt-controller/irq.h>
225 #include <dt-bindings/interrupt-controller/arm-gic.h>
228 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
233 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
239 clock-names = "gmu", "cxo", "axi", "memnoc";
243 interrupt-names = "hfi", "gmu";
245 power-domains = <&gpucc GPU_CX_GDSC>,
247 power-domain-names = "cx", "gx";
250 operating-points-v2 = <&gmu_opp_table>;