Lines Matching +full:sdm845 +full:- +full:dispcc
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SDM845 target
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SDM845 target.
20 - const: qcom,sdm845-mdss
25 reg-names:
28 power-domains:
33 - description: Display AHB clock from gcc
34 - description: Display core clock
36 clock-names:
38 - const: iface
39 - const: core
44 interrupt-controller: true
46 "#address-cells": true
48 "#size-cells": true
50 "#interrupt-cells":
55 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
56 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
62 - description: MDSS_CORE reset
65 "^display-controller@[0-9a-f]+$":
73 - const: qcom,sdm845-dpu
77 - description: Address offset and size for mdp register set
78 - description: Address offset and size for vbif register set
80 reg-names:
82 - const: mdp
83 - const: vbif
87 - description: Display ahb clock
88 - description: Display axi clock
89 - description: Display core clock
90 - description: Display vsync clock
92 clock-names:
94 - const: iface
95 - const: bus
96 - const: core
97 - const: vsync
102 power-domains:
105 operating-points-v2: true
106 opp-table:
127 - port@0
128 - port@1
131 - compatible
132 - reg
133 - reg-names
134 - clocks
135 - interrupts
136 - power-domains
137 - operating-points-v2
138 - ports
141 - compatible
142 - reg
143 - reg-names
144 - power-domains
145 - clocks
146 - interrupts
147 - interrupt-controller
148 - iommus
149 - ranges
154 - |
155 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
156 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
157 #include <dt-bindings/interrupt-controller/arm-gic.h>
158 #include <dt-bindings/power/qcom-rpmpd.h>
160 display-subsystem@ae00000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "qcom,sdm845-mdss";
165 reg-names = "mdss";
166 power-domains = <&dispcc MDSS_GDSC>;
169 <&dispcc DISP_CC_MDSS_MDP_CLK>;
170 clock-names = "iface", "core";
173 interrupt-controller;
174 #interrupt-cells = <1>;
180 display-controller@ae01000 {
181 compatible = "qcom,sdm845-dpu";
184 reg-names = "mdp", "vbif";
186 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
187 <&dispcc DISP_CC_MDSS_AXI_CLK>,
188 <&dispcc DISP_CC_MDSS_MDP_CLK>,
189 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
190 clock-names = "iface", "bus", "core", "vsync";
192 interrupt-parent = <&mdss>;
194 power-domains = <&rpmhpd SDM845_CX>;
195 operating-points-v2 = <&mdp_opp_table>;
198 #address-cells = <1>;
199 #size-cells = <0>;
204 remote-endpoint = <&dsi0_in>;
211 remote-endpoint = <&dsi1_in>;