Lines Matching +full:sc7180 +full:- +full:mdss
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7180 target
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SC7180 target.
20 - const: qcom,sc7180-mdss
25 reg-names:
26 const: mdss
28 power-domains:
33 - description: Display AHB clock from gcc
34 - description: Display AHB clock from dispcc
35 - description: Display core clock
37 clock-names:
39 - const: iface
40 - const: ahb
41 - const: core
46 interrupt-controller: true
48 "#address-cells": true
50 "#size-cells": true
52 "#interrupt-cells":
57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
63 - description: Interconnect path specifying the port ids for data bus
65 interconnect-names:
66 const: mdp0-mem
70 - description: MDSS_CORE reset
73 "^display-controller@[0-9a-f]+$":
81 - const: qcom,sc7180-dpu
85 - description: Address offset and size for mdp register set
86 - description: Address offset and size for vbif register set
88 reg-names:
90 - const: mdp
91 - const: vbif
95 - description: Display hf axi clock
96 - description: Display ahb clock
97 - description: Display rotator clock
98 - description: Display lut clock
99 - description: Display core clock
100 - description: Display vsync clock
102 clock-names:
104 - const: bus
105 - const: iface
106 - const: rot
107 - const: lut
108 - const: core
109 - const: vsync
114 power-domains:
117 operating-points-v2: true
118 opp-table:
139 - port@0
142 - compatible
143 - reg
144 - reg-names
145 - clocks
146 - interrupts
147 - power-domains
148 - operating-points-v2
149 - ports
152 - compatible
153 - reg
154 - reg-names
155 - power-domains
156 - clocks
157 - interrupts
158 - interrupt-controller
159 - iommus
160 - ranges
165 - |
166 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
167 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
168 #include <dt-bindings/interrupt-controller/arm-gic.h>
169 #include <dt-bindings/interconnect/qcom,sdm845.h>
170 #include <dt-bindings/power/qcom-rpmpd.h>
172 display-subsystem@ae00000 {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 compatible = "qcom,sc7180-mdss";
177 reg-names = "mdss";
178 power-domains = <&dispcc MDSS_GDSC>;
182 clock-names = "iface", "ahb", "core";
185 interrupt-controller;
186 #interrupt-cells = <1>;
189 interconnect-names = "mdp0-mem";
194 display-controller@ae01000 {
195 compatible = "qcom,sc7180-dpu";
199 reg-names = "mdp", "vbif";
207 clock-names = "bus", "iface", "rot", "lut", "core",
210 interrupt-parent = <&mdss>;
212 power-domains = <&rpmhpd SC7180_CX>;
213 operating-points-v2 = <&mdp_opp_table>;
216 #address-cells = <1>;
217 #size-cells = <0>;
222 remote-endpoint = <&dsi0_in>;
229 remote-endpoint = <&dp_in>;