Lines Matching +full:sc7280 +full:- +full:mdss
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - qcom,sc7180-dp
20 - qcom,sc7280-dp
21 - qcom,sc7280-edp
22 - qcom,sc8180x-dp
23 - qcom,sc8180x-edp
24 - qcom,sm8350-dp
29 - description: ahb register block
30 - description: aux register block
31 - description: link register block
32 - description: p0 register block
33 - description: p1 register block
40 - description: AHB clock to enable register access
41 - description: Display Port AUX clock
42 - description: Display Port Link clock
43 - description: Link interface clock between DP and PHY
44 - description: Display Port Pixel clock
46 clock-names:
48 - const: core_iface
49 - const: core_aux
50 - const: ctrl_link
51 - const: ctrl_link_iface
52 - const: stream_pixel
54 assigned-clocks:
56 - description: link clock source
57 - description: pixel clock source
59 assigned-clock-parents:
61 - description: phy 0 parent
62 - description: phy 1 parent
67 phy-names:
69 - const: dp
71 operating-points-v2:
74 opp-table: true
76 power-domains:
79 aux-bus:
80 $ref: /schemas/display/dp-aux-bus.yaml#
82 data-lanes:
83 $ref: /schemas/types.yaml#/definitions/uint32-array
89 "#sound-dai-cells":
92 vdda-0p9-supply:
94 vdda-1p2-supply:
109 - compatible
110 - reg
111 - interrupts
112 - clocks
113 - clock-names
114 - phys
115 - phy-names
116 - power-domains
117 - ports
123 - if:
128 - qcom,sc7280-edp
129 - qcom,sc8180x-edp
132 "#sound-dai-cells": false
137 aux-bus: false
141 - "#sound-dai-cells"
146 - |
147 #include <dt-bindings/interrupt-controller/arm-gic.h>
148 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
149 #include <dt-bindings/power/qcom-rpmpd.h>
151 displayport-controller@ae90000 {
152 compatible = "qcom,sc7180-dp";
158 interrupt-parent = <&mdss>;
165 clock-names = "core_iface", "core_aux",
169 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
172 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
175 phy-names = "dp";
177 #sound-dai-cells = <0>;
179 power-domains = <&rpmhpd SC7180_CX>;
182 #address-cells = <1>;
183 #size-cells = <0>;
188 remote-endpoint = <&dpu_intf0_out>;
195 remote-endpoint = <&typec>;