Lines Matching +full:0 +full:xae90200

61       - description: phy 0 parent
90     const: 0
92   vdda-0p9-supply:
100       port@0:
153         reg = <0xae90000 0x200>,
154               <0xae90200 0x200>,
155               <0xae90400 0xc00>,
156               <0xae91000 0x400>,
157               <0xae91400 0x400>;
172         assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
177         #sound-dai-cells = <0>;
183             #size-cells = <0>;
185             port@0 {
186                 reg = <0>;