Lines Matching +full:dt +full:- +full:bindings

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DSI Controller Device Tree Bindings
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
12   - Jitao Shi <jitao.shi@mediatek.com>
13   - Xinlei Lee <xinlei.lee@mediatek.com>
17   drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
21   - $ref: /schemas/display/dsi-controller.yaml#
26       - mediatek,mt2701-dsi
27       - mediatek,mt7623-dsi
28       - mediatek,mt8167-dsi
29       - mediatek,mt8173-dsi
30       - mediatek,mt8183-dsi
31       - mediatek,mt8186-dsi
39   power-domains:
44       - description: Engine Clock
45       - description: Digital Clock
46       - description: HS Clock
48   clock-names:
50       - const: engine
51       - const: digital
52       - const: hs
60   phy-names:
62       - const: dphy
68       port of an attached DSI panel or DSI-to-eDP encoder chip.
71   - compatible
72   - reg
73   - interrupts
74   - power-domains
75   - clocks
76   - clock-names
77   - phys
78   - phy-names
79   - port
84   - |
85     #include <dt-bindings/clock/mt8183-clk.h>
86     #include <dt-bindings/interrupt-controller/arm-gic.h>
87     #include <dt-bindings/interrupt-controller/irq.h>
88     #include <dt-bindings/power/mt8183-power.h>
89     #include <dt-bindings/phy/phy.h>
90     #include <dt-bindings/reset/mt8183-resets.h>
93         #address-cells = <2>;
94         #size-cells = <2>;
97             compatible = "mediatek,mt8183-dsi";
100             power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
104             clock-names = "engine", "digital", "hs";
107             phy-names = "dphy";
110                     remote-endpoint = <&panel_in>;