Lines Matching +full:zynq +full:- +full:7000

1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
15  - #clock-cells : Must be 1
16  - compatible : "xlnx,ps7-clkc"
17  - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
18  - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
19 		      (usually 33 MHz oscillators are used for Zynq platforms)
20  - clock-output-names : List of strings used to name the clock outputs. Shall be
24  - clocks : as described in the clock bindings
25  - clock-names : as described in the clock bindings
26  - fclk-enable : Bit mask to enable FCLKs statically at boot time.
32 The following strings are optional parameters to the 'clock-names' property in
34  - swdt_ext_clk
35  - gem0_emio_clk
36  - gem1_emio_clk
37  - mio_clk_XX		# with XX = 00..53
92 		#clock-cells = <1>;
93 		compatible = "xlnx,ps7-clkc";
94 		ps-clk-frequency = <33333333>;
96 		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
109 		clock-names = "gem1_emio_clk", "can_mio_clk_23";