Lines Matching +full:enable +full:- +full:frequency +full:- +full:shift
3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
23 "idlest" - contains the idlest register offset
24 "autoidle" - contains the autoidle register offset (OMAP2 only)
25 - ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
26 - ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
27 - ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
31 #clock-cells = <0>;
34 compatible = "ti,dra7-apll-clock";
38 #clock-cells = <0>;
39 compatible = "ti,omap2-apll-clock";
41 ti,bit-shift = <2>;
42 ti,idlest-shift = <8>;
43 ti,clock-frequency = <96000000>;