Lines Matching full:qoriq

1 * Clock Block on Freescale QorIQ Platforms
3 Freescale QorIQ chips take primary clocking input from the external
10 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
49 	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
50 	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
95 		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
117 	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
118 	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
119 	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
120 	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
121 	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
123 	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
125 	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
126 	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
128 	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
129 	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
130 	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
147 		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
156 			compatible = "fsl,qoriq-sysclk-1.0";
163 			compatible = "fsl,qoriq-core-pll-1.0";
171 			compatible = "fsl,qoriq-core-pll-1.0";
179 			compatible = "fsl,qoriq-core-mux-1.0";
188 			compatible = "fsl,qoriq-core-mux-1.0";
197 			compatible = "fsl,qoriq-platform-pll-1.0";