Lines Matching +full:sm8450 +full:- +full:dispcc

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8450
10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14   power domains on SM8450.
17     include/dt-bindings/clock/qcom,sm8450-dispcc.h
22       - qcom,sm8450-dispcc
27       - description: Board XO source
28       - description: Board Always On XO source
29       - description: Display's AHB clock
30       - description: sleep clock
31       - description: Byte clock from DSI PHY0
32       - description: Pixel clock from DSI PHY0
33       - description: Byte clock from DSI PHY1
34       - description: Pixel clock from DSI PHY1
35       - description: Link clock from DP PHY0
36       - description: VCO DIV clock from DP PHY0
37       - description: Link clock from DP PHY1
38       - description: VCO DIV clock from DP PHY1
39       - description: Link clock from DP PHY2
40       - description: VCO DIV clock from DP PHY2
41       - description: Link clock from DP PHY3
42       - description: VCO DIV clock from DP PHY3
44   '#clock-cells':
47   '#reset-cells':
50   '#power-domain-cells':
56   power-domains:
61   required-opps:
67   - compatible
68   - reg
69   - clocks
70   - '#clock-cells'
71   - '#reset-cells'
72   - '#power-domain-cells'
77   - |
78     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
79     #include <dt-bindings/clock/qcom,rpmh.h>
80     #include <dt-bindings/power/qcom-rpmpd.h>
81     clock-controller@af00000 {
82       compatible = "qcom,sm8450-dispcc";
92       #clock-cells = <1>;
93       #reset-cells = <1>;
94       #power-domain-cells = <1>;
95       power-domains = <&rpmhpd SM8450_MMCX>;
96       required-opps = <&rpmhpd_opp_low_svs>;