Lines Matching +full:meson8 +full:- +full:ddr +full:- +full:clkc

1 * Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
3 The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
8 - compatible: must be one of:
9 	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
10 	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
11 	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
14 - clocks: list of clock phandles, one for each entry in clock-names
15 - clock-names: should contain the following:
17   * "ddr_pll": the DDR PLL clock
21 - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
22 - reg: base address and size of the HHI system control register space.
26 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
30 dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
36 	clkc: clock-controller {
37 		compatible = "amlogic,meson8b-clkc";
38 		#clock-cells = <1>;
39 		#reset-cells = <1>;
47 		compatible = "amlogic,meson-uart";
50 		clocks = <&clkc CLKID_CLK81>;