Lines Matching +full:native +full:- +full:endian

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15   - Linus Walleij <linus.walleij@linaro.org>
19     pattern: '^bus@[0-9a-f]+$'
23       - enum:
24           - intel,ixp42x-expansion-bus-controller
25           - intel,ixp43x-expansion-bus-controller
26           - intel,ixp45x-expansion-bus-controller
27           - intel,ixp46x-expansion-bus-controller
28       - const: syscon
35   native-endian:
39       the SoC is running in big-endian or little-endian mode. Thus the
40       registers must always be accessed using native endianness.
42   "#address-cells":
48   "#size-cells":
52   dma-ranges: true
55   "^.*@[0-7],[0-9a-f]+$":
61       intel,ixp4xx-eb-t1:
66       intel,ixp4xx-eb-t2:
71       intel,ixp4xx-eb-t3:
76       intel,ixp4xx-eb-t4:
81       intel,ixp4xx-eb-t5:
86       intel,ixp4xx-eb-cycle-type:
92       intel,ixp4xx-eb-byte-access-on-halfword:
97       intel,ixp4xx-eb-hpi-hrdy-pol-high:
102       intel,ixp4xx-eb-mux-address-and-data:
107       intel,ixp4xx-eb-ahb-split-transfers:
112       intel,ixp4xx-eb-write-enable:
117       intel,ixp4xx-eb-byte-access:
124   - compatible
125   - reg
126   - native-endian
127   - "#address-cells"
128   - "#size-cells"
129   - ranges
130   - dma-ranges
135   - |
136     #include <dt-bindings/interrupt-controller/irq.h>
138         compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
140         native-endian;
141         #address-cells = <2>;
142         #size-cells = <1>;
145         dma-ranges = <0 0x0 0x50000000 0x01000000>,
148             compatible = "intel,ixp4xx-flash", "cfi-flash";
149             bank-width = <2>;
151             intel,ixp4xx-eb-t3 = <3>;
152             intel,ixp4xx-eb-cycle-type = <0>;
153             intel,ixp4xx-eb-byte-access-on-halfword = <1>;
154             intel,ixp4xx-eb-write-enable = <1>;
155             intel,ixp4xx-eb-byte-access = <0>;
160             interrupt-parent = <&gpio0>;
162             clock-frequency = <1843200>;
163             intel,ixp4xx-eb-t3 = <3>;
164             intel,ixp4xx-eb-cycle-type = <1>;
165             intel,ixp4xx-eb-write-enable = <1>;
166             intel,ixp4xx-eb-byte-access = <1>;