Lines Matching +full:mode +full:- +full:flag
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
20 - nvidia,tegra210-pmc
27 clock-names:
29 - const: pclk
30 - const: clk32k_in
39 Must contain an entry for each entry in clock-names.
40 See ../clocks/clocks-bindings.txt for details.
42 '#clock-cells':
50 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
53 '#interrupt-cells':
59 interrupt-controller: true
61 nvidia,invert-interrupt:
62 $ref: /schemas/types.yaml#/definitions/flag
69 nvidia,core-power-req-active-high:
70 $ref: /schemas/types.yaml#/definitions/flag
71 description: Core power request active-high.
73 nvidia,sys-clock-req-active-high:
74 $ref: /schemas/types.yaml#/definitions/flag
75 description: System clock request active-high.
77 nvidia,combined-power-req:
78 $ref: /schemas/types.yaml#/definitions/flag
81 nvidia,cpu-pwr-good-en:
82 $ref: /schemas/types.yaml#/definitions/flag
86 nvidia,suspend-mode:
90 The suspend mode that the platform should use.
91 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
92 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
93 Mode 2 is for LP2, CPU voltage off
95 nvidia,cpu-pwr-good-time:
99 nvidia,cpu-pwr-off-time:
103 nvidia,core-pwr-good-time:
104 $ref: /schemas/types.yaml#/definitions/uint32-array
106 <Oscillator-stable-time Power-stable-time>
109 nvidia,core-pwr-off-time:
113 nvidia,lp0-vec:
114 $ref: /schemas/types.yaml#/definitions/uint32-array
119 The AVP (Audio-Video Processor) is an ARM7 processor and
121 or resume from deep sleep mode. When the system is resumed
122 from the deep sleep mode, the warm boot code will restore
126 i2c-thermtrip:
129 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
130 hardware-triggered thermal reset will be enabled.
133 nvidia,i2c-controller-id:
141 nvidia,bus-addr:
145 nvidia,reg-addr:
149 nvidia,reg-data:
153 nvidia,pinmux-id:
161 - nvidia,i2c-controller-id
162 - nvidia,bus-addr
163 - nvidia,reg-addr
164 - nvidia,reg-data
173 represents a power-domain on the Tegra SoC that can be power-gated
176 "power-domains" property that is a phandle pointing to corresponding
181 Please refer to Tegra TRM for mode details on the powergate nodes to
182 use for each power-gate block inside Tegra.
208 "^[a-z0-9]+$":
217 for controlling a power-gate.
218 See ../clocks/clock-bindings.txt document for more details.
225 for controlling a power-gate.
228 '#power-domain-cells':
233 - clocks
234 - resets
235 - '#power-domain-cells'
240 "^[a-f0-9]+-[a-f0-9]+$":
246 and signaling voltage. A pad can be either in active or power down mode.
254 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
260 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
264 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
265 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
266 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
267 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
274 low-power-enable:
275 $ref: /schemas/types.yaml#/definitions/flag
276 description: Configure the pad into power down mode.
278 low-power-disable:
279 $ref: /schemas/types.yaml#/definitions/flag
280 description: Configure the pad into active mode.
282 power-source:
288 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
292 All of the listed Tegra210 pads except pex-cntrl support power
295 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
296 sdmmc3, spi, spi-hv, and uart.
299 - pins
303 core-domain:
311 operating-points-v2:
313 Should contain level, voltages and opp-supported-hw property.
314 The supported-hw is a bitfield indicating SoC speedo or process
317 "#power-domain-cells":
321 - operating-points-v2
322 - "#power-domain-cells"
326 core-supply:
331 - compatible
332 - reg
333 - clock-names
334 - clocks
335 - '#clock-cells'
340 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
341 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
342 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
345 - |
347 #include <dt-bindings/clock/tegra210-car.h>
348 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
349 #include <dt-bindings/soc/tegra-pmc.h>
352 compatible = "nvidia,tegra210-pmc";
354 core-supply = <®ulator>;
356 clock-names = "pclk", "clk32k_in";
357 #clock-cells = <1>;
359 nvidia,invert-interrupt;
360 nvidia,suspend-mode = <0>;
361 nvidia,cpu-pwr-good-time = <0>;
362 nvidia,cpu-pwr-off-time = <0>;
363 nvidia,core-pwr-good-time = <4587 3876>;
364 nvidia,core-pwr-off-time = <39065>;
365 nvidia,core-power-req-active-high;
366 nvidia,sys-clock-req-active-high;
368 pd_core: core-domain {
369 operating-points-v2 = <&core_opp_table>;
370 #power-domain-cells = <0>;
378 power-domains = <&pd_core>;
379 #power-domain-cells = <0>;
385 power-domains = <&pd_core>;
386 #power-domain-cells = <0>;