Lines Matching full:tegra

4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
7 title: Tegra Power Management Controller (PMC)
33       pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
34       input to Tegra.
45       Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
47       Tegra blink pad.
50       See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
138           "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
172       match the powergates on the Tegra SoC. Each powergate node
173       represents a power-domain on the Tegra SoC that can be power-gated
174       by the Tegra PMC.
179       not every powergate is applicable to all Tegra devices and the following
181       Please refer to Tegra TRM for mode details on the powergate nodes to
182       use for each power-gate block inside Tegra.
243       This is a Pad configuration node. On Tegra SOCs a pad is a set of
288           include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
306       The vast majority of hardware blocks of Tegra SoC belong to a
348     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
349     #include <dt-bindings/soc/tegra-pmc.h>