Lines Matching +full:mt8195 +full:- +full:mfgcfg
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
26 - enum:
27 - mediatek,mt8195-scp_adsp
28 - mediatek,mt8195-imp_iic_wrap_s
29 - mediatek,mt8195-imp_iic_wrap_w
30 - mediatek,mt8195-mfgcfg
31 - mediatek,mt8195-vppsys0
32 - mediatek,mt8195-wpesys
33 - mediatek,mt8195-wpesys_vpp0
34 - mediatek,mt8195-wpesys_vpp1
35 - mediatek,mt8195-vppsys1
36 - mediatek,mt8195-imgsys
37 - mediatek,mt8195-imgsys1_dip_top
38 - mediatek,mt8195-imgsys1_dip_nr
39 - mediatek,mt8195-imgsys1_wpe
40 - mediatek,mt8195-ipesys
41 - mediatek,mt8195-camsys
42 - mediatek,mt8195-camsys_rawa
43 - mediatek,mt8195-camsys_yuva
44 - mediatek,mt8195-camsys_rawb
45 - mediatek,mt8195-camsys_yuvb
46 - mediatek,mt8195-camsys_mraw
47 - mediatek,mt8195-ccusys
48 - mediatek,mt8195-vdecsys_soc
49 - mediatek,mt8195-vdecsys
50 - mediatek,mt8195-vdecsys_core1
51 - mediatek,mt8195-vencsys
52 - mediatek,mt8195-vencsys_core1
53 - mediatek,mt8195-apusys_pll
57 '#clock-cells':
61 - compatible
62 - reg
67 - |
68 scp_adsp: clock-controller@10720000 {
69 compatible = "mediatek,mt8195-scp_adsp";
71 #clock-cells = <1>;
74 - |
75 imp_iic_wrap_s: clock-controller@11d03000 {
76 compatible = "mediatek,mt8195-imp_iic_wrap_s";
78 #clock-cells = <1>;
81 - |
82 imp_iic_wrap_w: clock-controller@11e05000 {
83 compatible = "mediatek,mt8195-imp_iic_wrap_w";
85 #clock-cells = <1>;
88 - |
89 mfgcfg: clock-controller@13fbf000 {
90 compatible = "mediatek,mt8195-mfgcfg";
92 #clock-cells = <1>;
95 - |
96 vppsys0: clock-controller@14000000 {
97 compatible = "mediatek,mt8195-vppsys0";
99 #clock-cells = <1>;
102 - |
103 wpesys: clock-controller@14e00000 {
104 compatible = "mediatek,mt8195-wpesys";
106 #clock-cells = <1>;
109 - |
110 wpesys_vpp0: clock-controller@14e02000 {
111 compatible = "mediatek,mt8195-wpesys_vpp0";
113 #clock-cells = <1>;
116 - |
117 wpesys_vpp1: clock-controller@14e03000 {
118 compatible = "mediatek,mt8195-wpesys_vpp1";
120 #clock-cells = <1>;
123 - |
124 vppsys1: clock-controller@14f00000 {
125 compatible = "mediatek,mt8195-vppsys1";
127 #clock-cells = <1>;
130 - |
131 imgsys: clock-controller@15000000 {
132 compatible = "mediatek,mt8195-imgsys";
134 #clock-cells = <1>;
137 - |
138 imgsys1_dip_top: clock-controller@15110000 {
139 compatible = "mediatek,mt8195-imgsys1_dip_top";
141 #clock-cells = <1>;
144 - |
145 imgsys1_dip_nr: clock-controller@15130000 {
146 compatible = "mediatek,mt8195-imgsys1_dip_nr";
148 #clock-cells = <1>;
151 - |
152 imgsys1_wpe: clock-controller@15220000 {
153 compatible = "mediatek,mt8195-imgsys1_wpe";
155 #clock-cells = <1>;
158 - |
159 ipesys: clock-controller@15330000 {
160 compatible = "mediatek,mt8195-ipesys";
162 #clock-cells = <1>;
165 - |
166 camsys: clock-controller@16000000 {
167 compatible = "mediatek,mt8195-camsys";
169 #clock-cells = <1>;
172 - |
173 camsys_rawa: clock-controller@1604f000 {
174 compatible = "mediatek,mt8195-camsys_rawa";
176 #clock-cells = <1>;
179 - |
180 camsys_yuva: clock-controller@1606f000 {
181 compatible = "mediatek,mt8195-camsys_yuva";
183 #clock-cells = <1>;
186 - |
187 camsys_rawb: clock-controller@1608f000 {
188 compatible = "mediatek,mt8195-camsys_rawb";
190 #clock-cells = <1>;
193 - |
194 camsys_yuvb: clock-controller@160af000 {
195 compatible = "mediatek,mt8195-camsys_yuvb";
197 #clock-cells = <1>;
200 - |
201 camsys_mraw: clock-controller@16140000 {
202 compatible = "mediatek,mt8195-camsys_mraw";
204 #clock-cells = <1>;
207 - |
208 ccusys: clock-controller@17200000 {
209 compatible = "mediatek,mt8195-ccusys";
211 #clock-cells = <1>;
214 - |
215 vdecsys_soc: clock-controller@1800f000 {
216 compatible = "mediatek,mt8195-vdecsys_soc";
218 #clock-cells = <1>;
221 - |
222 vdecsys: clock-controller@1802f000 {
223 compatible = "mediatek,mt8195-vdecsys";
225 #clock-cells = <1>;
228 - |
229 vdecsys_core1: clock-controller@1803f000 {
230 compatible = "mediatek,mt8195-vdecsys_core1";
232 #clock-cells = <1>;
235 - |
236 vencsys: clock-controller@1a000000 {
237 compatible = "mediatek,mt8195-vencsys";
239 #clock-cells = <1>;
242 - |
243 vencsys_core1: clock-controller@1b000000 {
244 compatible = "mediatek,mt8195-vencsys_core1";
246 #clock-cells = <1>;
249 - |
250 apusys_pll: clock-controller@190f3000 {
251 compatible = "mediatek,mt8195-apusys_pll";
253 #clock-cells = <1>;