Lines Matching +full:encode +full:- +full:only
14 eBPF has 10 general purpose registers and a read-only frame pointer register,
15 all of which are 64-bits wide.
20 * R1 - R5: arguments for function calls
21 * R6 - R9: callee saved registers that function calls will preserve
22 * R10: read-only frame pointer to access stack
24 R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if
32 * the basic instruction encoding, which uses 64 bits to encode an instruction
33 * the wide instruction encoding, which appends a second 64-bit immediate value
48 -------------------
55 BPF_LD 0x00 non-standard load operations `Load and store instructions`_
59 BPF_ALU 0x04 32-bit arithmetic operations `Arithmetic and jump instructions`_
60 BPF_JMP 0x05 64-bit jump operations `Arithmetic and jump instructions`_
61 BPF_JMP32 0x06 32-bit jump operations `Arithmetic and jump instructions`_
62 BPF_ALU64 0x07 64-bit arithmetic operations `Arithmetic and jump instructions`_
69 ``BPF_JMP32``), the 8-bit 'opcode' field is divided into three parts:
82 BPF_K 0x00 use 32-bit immediate as source operand
90 -----------------------
92 ``BPF_ALU`` uses 32-bit wide operands while ``BPF_ALU64`` uses 64-bit wide operands for
100 BPF_SUB 0x10 dst -= src
135 The byte swap instructions use an instruction class of ``BPF_ALU`` and a 4-bit
139 only and do not use a separate source register or immediate value.
141 The 1-bit source operand field in the opcode is used to select what byte
165 -----------------
167 ``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for
174 BPF_JA 0x00 PC += off BPF_JMP only
183 BPF_EXIT 0x90 function / program return BPF_JMP only
198 8-bit 'opcode' field is divided as:
211 BPF_IMM 0x00 64-bit immediate instructions `64-bit immediate instructions`_
230 ---------------------------------
232 The ``BPF_MEM`` mode modifier is used to encode regular load and store
250 -----------------
259 * ``BPF_ATOMIC | BPF_W | BPF_STX`` for 32-bit operations
260 * ``BPF_ATOMIC | BPF_DW | BPF_STX`` for 64-bit operations
261 * 8-bit and 16-bit wide atomic operations are not supported.
263 The 'imm' field is used to encode the actual atomic operation.
264 Simple atomic operation use a subset of the values defined to encode
265 arithmetic operations in the 'imm' field to encode the atomic operation:
307 value that was at ``dst_reg + off`` before the operation is zero-extended
310 64-bit immediate instructions
311 -----------------------------
316 There is currently only one such instruction.
324 -------------------------------------