Lines Matching full:sme
6 order to support use of the ARM Scalable Matrix Extension (SME).
11 included in SME.
13 This document does not aim to describe the SME architecture or programmer's
15 model features for SME is included in Appendix A.
24 * The presence of SME is reported to userspace via HWCAP2_SME in the aux vector
25 AT_HWCAP2 entry. Presence of this flag implies the presence of the SME
27 described in this document. SME is reported in /proc/cpuinfo as "sme".
29 * Support for the execution of SME instructions in userspace can also be
31 instruction, and checking that the value of the SME field is nonzero. [3]
37 * There are a number of optional SME features, presence of these is reported
48 This list may be extended over time as the SME architecture evolves.
72 SME defines a second vector length similar to the SVE vector length which is
103 * All other SME state of a thread, including the currently configured vector
158 Some new prctl() calls are added to allow programs to manage the SME vector
194 EINVAL: SME not supported, invalid vector length requested, or
248 EINVAL: SME not supported.
335 will contain TPIDR2_EL0 on systems that support SME and will be read as
374 Appendix A. SME programmer's model (informative)
377 This section provides a minimal description of the additions made by SME to the
386 In A64 state, SME adds the following: