Lines Matching refs:initialised

206   level where the kernel image will be entered must be initialised by
220     - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
226       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
233       - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
234       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
243       ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
247       ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
255     - SCR_EL3.APK (bit 16) must be initialised to 0b1
256     - SCR_EL3.API (bit 17) must be initialised to 0b1
260     - HCR_EL2.APK (bit 40) must be initialised to 0b1
261     - HCR_EL2.API (bit 41) must be initialised to 0b1
267     - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
268     - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
269     - AMCNTENSET0_EL0 must be initialised to 0b1111
270     - AMCNTENSET1_EL0 must be initialised to a platform specific value
276     - AMCNTENSET0_EL0 must be initialised to 0b1111
277     - AMCNTENSET1_EL0 must be initialised to a platform specific value
285     - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
291     - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
297     - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
301     - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
307     - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
309     - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
314     - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
316     - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
318     - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
325     - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
327     - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
329     - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
334     - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
336     - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
338     - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
340     - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
343     - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
345     - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
347     - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
349     - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
355     - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
359     - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
365     - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
369     - HCR_EL2.ATA (bit 56) must be initialised to 0b1.