Lines Matching +full:in +full:- +full:kernel
10 is relevant to all public releases of the AArch64 Linux kernel.
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
15 level and exists only in secure mode. Both are architecturally optional.
19 is passed to the Linux kernel. This may include secure monitor and
28 3. Decompress the kernel image
29 4. Call the kernel image
33 ---------------------------
38 kernel will use for volatile data storage in the system. It performs
39 this in a machine dependent manner. (It may use internal algorithms
41 the RAM in the machine, or any other method the boot loader designer
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
51 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
52 using blocks of up to 2 megabytes in size, it must not be placed within
56 the 512 MB region starting at text_offset bytes below the kernel Image.
58 3. Decompress the kernel image
59 ------------------------------
63 The AArch64 kernel does not currently provide a decompressor and
70 4. Call the kernel image
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
81 u64 flags; /* kernel flags, little endian */
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
95 - when booting through EFI, code0/code1 are initially skipped.
100 - Prior to v3.17, the endianness of text_offset was not specified. In
101 these cases image_size is zero and text_offset is 0x80000 in the
102 endianness of the kernel. Where image_size is non-zero image_size is
103 little-endian and must be respected. Where image_size is zero,
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
110 Bit 0 Kernel endianness. 1 if BE, 0 if LE.
111 Bit 1-2 Kernel Page size.
113 * 0 - Unspecified.
114 * 1 - 4K
115 * 2 - 16K
116 * 3 - 64K
117 Bit 3 Kernel physical placement
124 2MB aligned base may be anywhere in physical
126 Bits 4-63 Reserved.
129 - When image_size is zero, a bootloader should attempt to keep as much
130 memory as possible free for use by the kernel immediately after the
131 end of the kernel image. The amount of space required will vary
135 address anywhere in usable system RAM and called there. The region
137 special significance to the kernel, and may be used for other purposes.
139 use by the kernel.
144 If an initrd/initramfs is passed to the kernel at boot, it must reside
145 entirely within a 1 GB aligned physical memory window of up to 32 GB in
146 size that fully covers the kernel Image as well.
148 Any memory described to the kernel (even that below the start of the
149 image) which is not marked as reserved from the kernel (e.g., with a
150 memreserve region in the device tree) will be considered as available to
151 the kernel.
153 Before jumping into the kernel, the following conditions must be met:
155 - Quiesce all DMA capable devices so that memory does not get
159 - Primary CPU general-purpose register settings:
161 - x0 = physical address of device tree blob (dtb) in system RAM.
162 - x1 = 0 (reserved for future use)
163 - x2 = 0 (reserved for future use)
164 - x3 = 0 (reserved for future use)
166 - CPU mode
168 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
170 The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
171 to have access to the virtualisation extensions), or in EL1.
173 - Caches, MMUs
178 entries corresponding to the loaded kernel image.
180 The address range corresponding to the loaded kernel image must be
181 cleaned to the PoC. In the presence of a system cache or other
189 - Architected timers
193 kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
196 - Coherency
198 All CPUs to be booted by the kernel must be part of the same coherency
199 domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
203 - System registers
206 level where the kernel image will be entered must be initialised by
207 software at a higher exception level to prevent execution in an UNKNOWN
211 - If EL3 is present:
213 - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
215 - The value of SCR_EL3.FIQ must be the same as the one present at boot
216 time whenever the kernel is executing.
218 - If EL3 is present and the kernel is entered at EL2:
220 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
222 For systems with a GICv3 interrupt controller to be used in v3 mode:
223 - If EL3 is present:
225 - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
226 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
227 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
228 all CPUs the kernel is executing on, and must stay constant
229 for the lifetime of the kernel.
231 - If the kernel is entered at EL1:
233 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
234 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
236 - The DT or ACPI tables must describe a GICv3 interrupt controller.
238 For systems with a GICv3 interrupt controller to be used in
241 - If EL3 is present:
245 - If the kernel is entered at EL1:
249 - The DT or ACPI tables must describe a GICv2 interrupt controller.
253 - If EL3 is present:
255 - SCR_EL3.APK (bit 16) must be initialised to 0b1
256 - SCR_EL3.API (bit 17) must be initialised to 0b1
258 - If the kernel is entered at EL1:
260 - HCR_EL2.APK (bit 40) must be initialised to 0b1
261 - HCR_EL2.API (bit 41) must be initialised to 0b1
265 - If EL3 is present:
267 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
268 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
269 - AMCNTENSET0_EL0 must be initialised to 0b1111
270 - AMCNTENSET1_EL0 must be initialised to a platform specific value
274 - If the kernel is entered at EL1:
276 - AMCNTENSET0_EL0 must be initialised to 0b1111
277 - AMCNTENSET1_EL0 must be initialised to a platform specific value
283 - If EL3 is present and the kernel is entered at EL2:
285 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
289 - If EL3 is present and the kernel is entered at EL2:
291 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
295 - If EL3 is present:
297 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
299 - If EL2 is present and the kernel is entered at EL1:
301 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
305 - if EL3 is present:
307 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
309 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
310 kernel is executed on.
312 - If the kernel is entered at EL1 and EL2 is present:
314 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
316 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
318 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
319 kernel will execute on.
323 - If EL3 is present:
325 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
327 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
329 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
330 kernel will execute on.
332 - If the kernel is entered at EL1 and EL2 is present:
334 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
336 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
338 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
340 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
341 kernel will execute on.
343 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
345 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
347 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
349 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
353 - If EL3 is present:
355 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
357 - If the kernel is entered at EL1 and EL2 is present:
359 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
363 - If EL3 is present:
365 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
367 - If the kernel is entered at EL1 and EL2 is present:
369 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
373 enter the kernel in the same exception level. Where the values documented
378 The boot loader is expected to enter the kernel on each CPU in the
381 - The primary CPU must jump directly to the first instruction of the
382 kernel image. The device tree blob passed by this CPU must contain
383 an 'enable-method' property for each cpu node. The supported
384 enable-methods are described below.
387 properties and insert them into the blob prior to kernel entry.
389 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
390 property in their cpu node. This property identifies a
391 naturally-aligned 64-bit zero-initalised memory location.
393 These CPUs should spin outside of the kernel in a reserved area of
394 memory (communicated to the kernel by a /memreserve/ region in the
395 device tree) polling their cpu-release-addr location, which must be
396 contained in the reserved region. A wfe instruction may be inserted
397 to reduce the overhead of the busy-loop and a sev will be issued by
399 cpu-release-addr returns a non-zero value, the CPU must jump to this
400 value. The value will be written as a single 64-bit little-endian
404 - CPUs with a "psci" enable method should remain outside of
405 the kernel (i.e. outside of the regions of memory described to the
406 kernel in the memory node, or in a reserved area of memory described
407 to the kernel by a /memreserve/ region in the device tree). The
408 kernel will issue CPU_ON calls as described in ARM document number ARM
410 processors") to bring CPUs into the kernel.
412 The device tree should contain a 'psci' node, as described in
415 - Secondary CPU general-purpose register settings
417 - x0 = 0 (reserved for future use)
418 - x1 = 0 (reserved for future use)
419 - x2 = 0 (reserved for future use)
420 - x3 = 0 (reserved for future use)