Lines Matching full:must
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
52 using blocks of up to 2 megabytes in size, it must not be placed within
53 any 2M region which must be mapped with any specific attributes.
103 little-endian and must be respected. Where image_size is zero,
134 The Image must be placed text_offset bytes from a 2MB aligned base
138 At least image_size bytes from the start of the image must be free for
144 If an initrd/initramfs is passed to the kernel at boot, it must reside
153 Before jumping into the kernel, the following conditions must be met:
168 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
170 The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
175 The MMU must be off.
177 The instruction cache may be on or off, and must not hold any stale
180 The address range corresponding to the loaded kernel image must be
185 operations must be configured and may be enabled.
187 operations (not recommended) must be configured and disabled.
191 CNTFRQ must be programmed with the timer frequency and CNTVOFF must
193 kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
198 All CPUs to be booted by the kernel must be part of the same coherency
206 level where the kernel image will be entered must be initialised by
213 - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
215 - The value of SCR_EL3.FIQ must be the same as the one present at boot
220 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
225 - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
226 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
227 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
228 all CPUs the kernel is executing on, and must stay constant
233 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
234 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
236 - The DT or ACPI tables must describe a GICv3 interrupt controller.
243 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
247 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
249 - The DT or ACPI tables must describe a GICv2 interrupt controller.
255 - SCR_EL3.APK (bit 16) must be initialised to 0b1
256 - SCR_EL3.API (bit 17) must be initialised to 0b1
260 - HCR_EL2.APK (bit 40) must be initialised to 0b1
261 - HCR_EL2.API (bit 41) must be initialised to 0b1
267 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
268 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
269 - AMCNTENSET0_EL0 must be initialised to 0b1111
270 - AMCNTENSET1_EL0 must be initialised to a platform specific value
276 - AMCNTENSET0_EL0 must be initialised to 0b1111
277 - AMCNTENSET1_EL0 must be initialised to a platform specific value
285 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
291 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
297 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
301 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
307 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
309 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
314 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
316 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
318 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
325 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
327 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
329 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
334 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
336 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
338 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
340 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
343 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
345 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
347 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
349 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
355 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
359 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
365 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
369 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
372 timers, coherency and system registers apply to all CPUs. All CPUs must
381 - The primary CPU must jump directly to the first instruction of the
382 kernel image. The device tree blob passed by this CPU must contain
389 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
395 device tree) polling their cpu-release-addr location, which must be
399 cpu-release-addr returns a non-zero value, the CPU must jump to this
401 value, so CPUs must convert the read value to their native endianness