Lines Matching +full:dma +full:- +full:router
1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
15 direct memory access controllers (DMA).
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
18 request routing capabilities are enhanced by a DMA request multiplexer
23 STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA
24 controller (STM32MP1 counts two STM32 DMA controllers) channels.
26 **STM32 DMA**
28 STM32 DMA is mainly used to implement central data buffer storage (usually in
35 STM32 MDMA (Master DMA) is mainly used to manage direct data transfers between
37 hierarchical structure that uses STM32 DMA as first level data buffer
39 DMA with better performance. As a AXI/AHB master, STM32 MDMA can take control
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
49 STM32 DMA has a circular Double Buffer Mode (DBM). At each end of transaction
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
51 (configured with DMA_SxSM0AR and DMA_SxM1AR) are swapped and the DMA data
54 the STM32 DMA transfer.
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
60 case, the linked-list loops on to create a circular MDMA transfer.
62 STM32 MDMA has direct connections with STM32 DMA. This enables autonomous
64 resources and bus congestion. Transfer Complete signal of STM32 DMA channel
66 by the STM32 DMA by writing to its Interrupt Clear register (whose address is
69 .. table:: STM32 MDMA interconnect table with STM32 DMA
71 +--------------+----------------+-----------+------------+
72 | STM32 DMAMUX | STM32 DMA | STM32 DMA | STM32 MDMA |
78 +--------------+----------------+-----------+------------+
80 +--------------+----------------+-----------+------------+
82 +--------------+----------------+-----------+------------+
84 +--------------+----------------+-----------+------------+
86 +--------------+----------------+-----------+------------+
88 +--------------+----------------+-----------+------------+
90 +--------------+----------------+-----------+------------+
92 +--------------+----------------+-----------+------------+
94 +--------------+----------------+-----------+------------+
96 +--------------+----------------+-----------+------------+
98 +--------------+----------------+-----------+------------+
100 +--------------+----------------+-----------+------------+
102 +--------------+----------------+-----------+------------+
104 +--------------+----------------+-----------+------------+
106 +--------------+----------------+-----------+------------+
108 +--------------+----------------+-----------+------------+
110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
112 Due to STM32 DMA legacy (within microcontrollers), STM32 DMA performances are
114 between STM32 DMA and STM32 MDMA. This buffer is split in two equal periods
115 and STM32 DMA uses one period while STM32 MDMA uses the other period
119 dma[1:2]-tcf[0:7]
120 .----------------.
122 | STM32 DMA | / __|>_ \ | STM32 MDMA |
123 |------------| | / \ | |------------|
124 | DMA_SxM0AR |<=>| | SRAM | |<=>| []-[]...[] |
128 STM32 DMA-MDMA chaining uses (struct dma_slave_config).peripheral_config to
133 * the address of the STM32 DMA register to clear the Transfer Complete
135 * the mask of the Transfer Complete interrupt flag of the STM32 DMA channel.
137 Device Tree updates for STM32 DMA-MDMA chaining support
138 -------------------------------------------------------
147 my_foo_device_dma_pool: dma-sram@0 {
154 STM32 DMA and STM32 MDMA can work simultaneously, on each buffer of the
156 If the SRAM period is greater than the expected DMA transfer, then STM32 DMA
171 **2. Allocate a STM32 DMA channel and a STM32 MDMA channel**
174 the one you should already have for "classic" DMA operation.
177 the DMA controller to use is the MDMA controller's one.
183 dmas = <&dmamux1 ...>, // STM32 DMA channel
196 3. A 32bit mask specifying the DMA channel configuration : source and
201 request: it will be overwritten by MDMA driver, with the DMA channel
206 request: it will be overwritten by MDMA driver, with the DMA channel
210 Driver updates for STM32 DMA-MDMA chaining support in foo driver
211 ----------------------------------------------------------------
217 STM32 DMA transfer (where memory address targets now the SRAM buffer instead
229 * allocated from the pool for DMA usage, and the length of the period,
245 /* Create sg table for STM32 DMA channel */
248 dev_err(dev, "DMA sg table alloc failed\n");
254 s->dma_address = sram_buf;
260 s->dma_address += sram_period;
276 len -= bytes;
293 configure STM32 DMA channel. You just have to take care of DMA addresses,
297 STM32 DMA driver will check (struct dma_slave_config).peripheral_size to
298 determine if chaining is being used or not. If it is used, then STM32 DMA
305 configure STM32 MDMA channel. Take care of DMA addresses, the device address
308 DMA operation. Use the previous (struct dma_slave_config).peripheral_size
309 and .peripheral_config that have been updated by STM32 DMA driver, to set
329 mdma_conf.peripheral_size = dma_conf.peripheral_size; // <- dma_conf
330 mdma_conf.peripheral_config = dma_config.peripheral_config; // <- dma_conf
334 **2. Get a descriptor for STM32 DMA channel transaction**
336 In the same way you get your descriptor for your "classic" DMA operation,
344 If you previously get descriptor (for STM32 DMA) with
365 * DMA_MEM_TO_DEV: set the callback on the "DMA" descriptor
371 As STM32 MDMA channel transfer is triggered by STM32 DMA, you must issue
372 STM32 MDMA channel before STM32 DMA channel.
377 Don't forget to terminate both channels. STM32 DMA channel is configured in
378 cyclic Double-Buffer mode so it won't be disabled by HW, you need to terminate
382 **STM32 DMA-MDMA chaining DMA_MEM_TO_DEV special case**
384 STM32 DMA-MDMA chaining in DMA_MEM_TO_DEV is a special case. Indeed, the
385 STM32 MDMA feeds the SRAM buffer with the DDR data, and the STM32 DMA reads
387 SRAM buffer when the STM32 DMA starts to read.
389 A trick could be pausing the STM32 DMA channel (that will raise a Transfer
391 by the STM32 DMA could be "wrong". The proper way is to prepare the first SRAM
395 Due to this complexity, rather use the STM32 DMA-MDMA chaining for
396 DMA_DEV_TO_MEM and keep the "classic" DMA usage for DMA_MEM_TO_DEV, unless
400 ---------
406 dealing with STM32 DMAMUX, STM32 DMA and STM32 MDMA.
408 .. _STM32MP1: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
409 …24: https://www.st.com/resource/en/application_note/an5224-stm32-dmamux-the-dma-request-router-stm…
410 …st.com/resource/en/application_note/dm00046011-using-the-stm32f2-stm32f4-and-stm32f7-series-dma-co…
411 …s://www.st.com/resource/en/application_note/an5001-stm32cube-expansion-package-for-stm32h7-series-…
415 - Amelie Delaunay <amelie.delaunay@foss.st.com>