Lines Matching +full:m +full:- +full:mode

6   POW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - power
7   RPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse power
8   POL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2)
10   LOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10
11   LGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e
12   EXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponent
13   SIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sine
14   COS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosine
15   TAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangent
16   ASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsine
17   ACS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arccosine
18   ATN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arctangent
39 ----------------
42 default, but rounding to + or - infinity or round to zero are also allowed.
43 Many architectures allow the rounding mode to be specified by modifying bits
45 the rounding mode one must specify it with each instruction.
49 bits describing the rounding mode.  The emulator could be altered to
50 examine a flag, which if set forced it to ignore the rounding mode in
51 the instruction, and use the mode specified in the bits in the FPCR.
63  implementations: it is there to control the hardware in an implementation-
65  mode of the ARM is not permitted to use this register (since the right is
67  instructions will trap if tried in user mode.
72 		-- Russell.