Lines Matching full:these

15 Description:	These files show with which CPLD versions have been burned
34 Description:	These files show with which CPLD versions have been burned
43 Description:	These files enable and disable the access to the JTAG domain.
66 Description:	These files allow asserting system power cycling, switching
93 Description:	These files show the system reset cause, as following: power
110 Description:	These files show the system reset cause, as following: ComEx
123 Description:	These files show with which CPLD versions have been burned
137 Description:	These files show the system reset cause, as following:
152 Description:	These files show system static topology identification
165 Description:	These files show the system reset causes, as following: reset
221 Description:	These files show with which CPLD part numbers and minor
261 Description:	These files allow line cards enable state control.
279 Description:	These files switching line cards power on and off.
297 Description:	These files clear line card reset bit enforced by ASIC, when it
341 Description:	These files switching power supply units on and off.
374 Description:	These files show with which CPLD major and minor versions
385 Description:	These files show with which FPGA major and minor versions
414 Description:	These files show the line reset cause, as following: power
428 Description:	These files allow CPLD and FPGA burning. Value 1 in file means burning
430 		If the system is in locked-down mode writing these files will
432 		The purpose of these files to allow line card CPLD and FPGA
442 Description:	These files allow to power on/off all QSFP ports and whole line card.
452 Description:	These files allow gearboxes and FPGA SPI flash burning.
454 		If the system is in locked-down mode writing these files will
456 		The purpose of these files to allow line card Gearboxes and FPGA
466 Description:	These files provide the maximum powered required for line card
521 Description:	These files allow to each of ASICs by writing 1.