Lines Matching full:that
4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
14 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line…
24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects…
34 …on which likely indicates back pressure from L2Q. It also counts requests that would have gone dir…
54 …"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That …
92 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
104 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
116 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
146 …"PublicDescription": "Counts the number of memory uops retired that is either a loads or a store o…
158 "PublicDescription": "Counts load uops retired that hit the L1 data cache.",
164 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
170 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
176 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
182 "PublicDescription": "Counts load uops retired that miss the L1 data cache.",
188 "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
194 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
200 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
206 …that when the load address was checked by other caching agents (typically another processor) in th…
218 …that the load found its data while that data was in the process of being brought into the L1 cache…
224 "BriefDescription": "Loads retired that hit WCB (Precise event capable)",
236 "BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
241 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. …
249 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
254 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache w…
262 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache w…
267 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache w…
275 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache w…
280 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L…
288 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L…
293 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. R…
301 …read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
306 …"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the …
314 …"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L…
319 …"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the …
327 …"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L…
332 …"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the …
340 …"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L…
345 …"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss…
353 …"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss …
358 …"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L…
366 …"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2…
371 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_O…
379 "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.",
384 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hi…
392 …"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit…
397 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hi…
405 …"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit…
410 …"PublicDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a…
418 …"BriefDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a …
423 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF…
431 "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.",
436 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. …
444 … "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.",
449 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache w…
457 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache wi…
462 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache w…
470 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache wi…
475 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L…
483 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2…
488 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. R…
496 … "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.",
501 …"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop …
509 …"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop h…
514 …"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop …
522 …"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop h…
527 …"PublicDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with…
535 …"BriefDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with …
540 …"PublicDescription": "Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_…
548 "BriefDescription": "Counts requests to the uncore subsystem that hit the L2 cache.",
553 …"PublicDescription": "Counts requests to the uncore subsystem that have any transaction responses …
561 …"BriefDescription": "Counts requests to the uncore subsystem that have any transaction responses f…
566 …unts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. …
574 …unts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.",
579 …unts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. R…
587 …ounts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.",
592 …che line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. …
600 …che line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.",
605 …che line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache w…
613 …che line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache w…
618 …che line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache w…
626 …che line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache w…
631 …che line data writes to uncacheable write combining (USWC) memory region that true miss for the L…
639 …che line data writes to uncacheable write combining (USWC) memory region that true miss for the L…
644 …che line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. R…
652 …ache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.",
657 …unts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. …
665 …unts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache.",
670 …unts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache w…
678 …unts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache w…
683 …unts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache w…
691 …unts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache w…
696 …unts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L…
704 …unts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L…
709 …unts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. R…
717 …ounts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache.",
722 …ion": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache. …
730 …ion": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache.",
735 …ion": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache w…
743 …ion": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache w…
748 …ion": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache w…
756 …ion": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache w…
761 …ion": "Counts data cache lines requests by software prefetch instructions that true miss for the L…
769 …ion": "Counts data cache lines requests by software prefetch instructions that true miss for the L…
774 …ion": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache. R…
782 …tion": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache.",
787 …te combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. …
795 …te combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache.",
800 …te combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache w…
808 …te combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache w…
813 …te combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache w…
821 …te combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache w…
826 …te combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L…
834 …te combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L…
839 …te combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. R…
847 …ite combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache.",
852 …"PublicDescription": "Counts bus lock and split lock requests that have any transaction responses …
860 …"BriefDescription": "Counts bus lock and split lock requests that have any transaction responses f…
865 …ble (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. …
873 …ble (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache.",
878 …ta in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. …
886 …ta in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.",
891 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. …
899 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.",
904 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache w…
912 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache w…
917 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache w…
925 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache w…
930 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L…
938 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L…
943 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. R…
951 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.",
956 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. …
964 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.",
969 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache w…
977 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache w…
982 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache w…
990 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache w…
995 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L…
1003 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L…
1008 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. R…
1016 …n": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.",
1021 …s the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. …
1029 …s the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.",
1034 …s the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache w…
1042 …s the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache w…
1047 …s the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache w…
1055 …s the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache w…
1060 …s the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L…
1068 …s the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L…
1073 …s the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. R…
1081 …ts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache.",
1086 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are…
1094 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are…
1099 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that mis…
1107 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that mis…
1112 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that mis…
1120 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that mis…
1125 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that tru…
1133 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that tru…
1138 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit…
1146 …demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit…
1151 …for ownership (RFO) requests generated by a write to full data cache line that are outstanding, pe…
1159 …for ownership (RFO) requests generated by a write to full data cache line that are outstanding, pe…
1164 …for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. …
1172 …for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.",
1177 …for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache w…
1185 …for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache w…
1190 …for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache w…
1198 …for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache w…
1203 …for ownership (RFO) requests generated by a write to full data cache line that true miss for the L…
1211 …for ownership (RFO) requests generated by a write to full data cache line that true miss for the L…
1216 …for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. R…
1224 … for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.",
1229 …"PublicDescription": "Counts demand cacheable data reads of full cache lines that are outstanding,…
1237 …"BriefDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, …
1242 …"PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cach…
1250 …"BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache…
1255 …"PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cach…
1263 …"BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache…
1268 …"PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cach…
1276 …"BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache…
1281 …"PublicDescription": "Counts demand cacheable data reads of full cache lines that true miss for th…
1289 …"BriefDescription": "Counts demand cacheable data reads of full cache lines that true miss for the…
1294 …"PublicDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache…
1302 …"BriefDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache.…