Lines Matching full:or
5 …he was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (…
6 …) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to ei…
11 …ache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (…
12 …) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to ei…
17 …essor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due …
18 …loaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loa…
24 …ta cache was reloaded from local core's L2 due to either only demand loads or demand loads plus pr…
36 …a localtion other than the local core's L2 due to either only demand loads or demand loads plus pr…
42 …cal core's L2 with load hit store conflict due to either only demand loads or demand loads plus pr…
48 …rom local core's L2 with dispatch conflict due to either only demand loads or demand loads plus pr…
54 …t without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus pr…
60 …aded from local core's L2 without conflict due to either only demand loads or demand loads plus pr…
66 …ta cache was reloaded from local core's L3 due to either only demand loads or demand loads plus pr…
78 …a localtion other than the local core's L3 due to either only demand loads or demand loads plus pr…
84 …rom local core's L3 with dispatch conflict due to either only demand loads or demand loads plus pr…
90 …thout dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus pr…
96 …aded from local core's L3 without conflict due to either only demand loads or demand loads plus pr…
102 …as reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus pr…
107 …s data cache was reloaded either shared or modified data from another core's L2/L3 on a different …
108 …ded either shared or modified data from another core's L2/L3 on a different chip (remote or distan…
113 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a…
114 …e was reloaded either shared or modified data from another core's L2/L3 on the same chip due to ei…
119 …ache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (R…
120 …(M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to eith…
125 … cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (R…
126 …(S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to eith…
131 "BriefDescription": "Tablwalk Cycles (could be 1 or 2 active)",
149 "BriefDescription": "L1 data cache reloaded for demand or prefetch",