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1 This document provides background reading for memory models and related
6 Hardware manuals and models
18 o Intel Corporation (Ed.). 2002. "Intel 64 and IA-32 Architectures
22 and Magnus O. Myreen. 2010. "x86-TSO: A Rigorous and Usable
29 o ARM Ltd. (Ed.). 2009. "ARM Barrier Litmus Tests and Cookbook".
32 o Susmit Sarkar, Peter Sewell, Jade Alglave, Luc Maranget, and
35 Language Design and Implementation (PLDI ’11). ACM, New York,
39 Peter Sewell, Luc Maranget, Jade Alglave, and Derek Williams.
40 2012. "Synchronising C/C++ and POWER". In Proceedings of the 33rd
41 ACM SIGPLAN Conference on Programming Language Design and
53 Sarkar, Ali Sezgin, Luc Maranget, Will Deacon, and Peter
55 Concurrency and ISA". In Proceedings of the 43rd Annual ACM
60 Luc Maranget, Kathryn E. Gray, Ali Sezgin, Mark Batty, and Peter
62 and SC". In Proceedings of the 44th ACM SIGPLAN Symposium on
67 Susmit Sarkar, and Peter Sewell. 2018. "Simplifying ARM concurrency:
68 multicopy-atomic axiomatic and operational models for ARMv8". In
76 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
77 Alan Stern. 2018. "Frightening small children and disconcerting
80 Programming Languages and Operating Systems (ASPLOS 2018). ACM,
83 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
87 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
99 o Jade Alglave, Luc Maranget, and Michael Tautschnig. 2014. "Herding
100 Cats: Modelling, Simulation, Testing, and Data Mining for Weak
104 o Jade Alglave, Patrick Cousot, and Luc Maranget. 2016. "Syntax and
112 o Paul E. McKenney, Ulrich Weigand, Andrea Parri, and Boqun