Lines Matching refs:P1
121 P1()
132 CPU and P1() represents the read() routine running on another. The
134 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
153 A memory model will predict what values P1 might obtain for its loads
162 instance, P1 might run entirely before P0 begins, in which case r1 and
163 r2 will both be 0 at the end. Or P0 might run entirely before P1
167 routines run concurrently. One possibility is that P1 runs after P0's
169 will again both be 0. (If P1 had been designed to read buf
196 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
199 P1 loads from flag before loading from buf, since CPUs execute
202 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
209 Since an instruction (in this case, P1's store to flag) cannot
235 P1()
271 X: P1 loads 1 from flag executes before
272 Y: P1 loads 0 from buf executes before
517 P1()
541 P1()
548 If r1 = 0x56781234 (little-endian!) at the end, then P1 must have read
649 P1()
664 READ_ONCE() in P1, on Itanium it sometimes could end up with r1 = 5
1085 P1()
1094 can malfunction on Alpha systems (notice that P1 uses an ordinary load
1099 smp_wmb() forces P0's store to x to propagate to P1 before the store
1100 to ptr does. And since P1 can't execute its second load
1102 first load, the value x = 1 must have propagated to P1 before the
1106 stores do reach P1's local cache in the proper order, it can happen
1109 value may not become available for P1's CPU to read until after the
1119 between P1's two loads when the kernel is compiled for the Alpha
1128 P1()
1137 then we would never get r1 = &x and r2 = 0. By the time P1 executed
1209 P1()
1219 event, because P1's store came after P0's store in x's coherence
1220 order, and P1's store propagated to P0 before P0's load executed.
1235 P1()
1245 because P1's store overwrote the value read by P0's first load, and
1246 P1's store propagated to P0 before P0's second load executed.
1261 P1()
1272 from P1's second load to its first (backwards!). The reason is
1273 similar to the previous examples: The value P1 loads from buf gets
1275 to buf will propagate to P1 before the store to flag does, and the
1276 store to flag propagates to P1 before P1 reads flag.
1279 P1 must execute its second load before the first. Indeed, if the load
1281 have propagated to P1 by the time P1's load from buf executed, so r2
1286 But what if we put an smp_rmb() fence between P1's loads? The fence
1313 P1()
1330 overwritten by P1's store since x = 2 at the end (a coe link), the
1331 smp_wmb() ensures that P1's store to x propagates to P2 before the
1401 P1()
1410 If r0 = 0 at the end then there is a pb link from P0's load to P1's
1411 load: an fre link from P0's load to P1's store (which overwrites the
1412 value read by P0), and a strong fence between P1's store and its load.
1417 Similarly, if r1 = 0 at the end then there is a pb link from P1's load
1470 P1()
1481 means that P0's store to x propagated to P1 before P1 called
1483 P1's grace period, contrary to part (2) of the Guarantee. On the
1485 end of the critical section, did not propagate to P1 before the end of
1661 P1()
1672 P1's load at W reads from, so we have W ->fre Y. Since S ->po W and
1676 If r1 = 1 at the end then P1's load at Z reads from P0's store at X,
1699 P1()
1726 P0 P1 P2
1744 section in P0 both starts before P1's grace period does and ends
1745 before it does, and the critical section in P2 both starts after P1's
1817 P1()
1869 P1()
1888 If r1 = 1 at the end then the spin_lock() in P1 must have read from
1994 P1()
2005 you it is not, but the model won't mention that this is because P1