83 static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg)  in zx_tdm_readl()  argument
85 	return readl_relaxed(tdm->regbase + reg);  in zx_tdm_readl()
88 static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)  in zx_tdm_writel()  argument
90 	writel_relaxed(val, tdm->regbase + reg);  in zx_tdm_writel()
93 static void zx_tdm_tx_en(struct zx_tdm_info *tdm, bool on)  in zx_tdm_tx_en()  argument
97 	val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);  in zx_tdm_tx_en()
102 	zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);  in zx_tdm_tx_en()
105 static void zx_tdm_rx_en(struct zx_tdm_info *tdm, bool on)  in zx_tdm_rx_en()  argument
109 	val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);  in zx_tdm_rx_en()
114 	zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);  in zx_tdm_rx_en()
117 static void zx_tdm_tx_dma_en(struct zx_tdm_info *tdm, bool on)  in zx_tdm_tx_dma_en()  argument
121 	val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);  in zx_tdm_tx_dma_en()
127 	zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);  in zx_tdm_tx_dma_en()
130 static void zx_tdm_rx_dma_en(struct zx_tdm_info *tdm, bool on)  in zx_tdm_rx_dma_en()  argument
134 	val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);  in zx_tdm_rx_dma_en()
140 	zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);  in zx_tdm_rx_dma_en()
165 	struct zx_tdm_info *tdm = snd_soc_dai_get_drvdata(cpu_dai);  in zx_tdm_set_fmt()  local
168 	val = zx_tdm_readl(tdm, REG_TIMING_CTRL);  in zx_tdm_set_fmt()
174 		tdm->master = 1;  in zx_tdm_set_fmt()
178 		tdm->master = 0;  in zx_tdm_set_fmt()
187 	zx_tdm_writel(tdm, REG_TIMING_CTRL, val);  in zx_tdm_set_fmt()
196 	struct zx_tdm_info *tdm = snd_soc_dai_get_drvdata(socdai);  in zx_tdm_hw_params()  local
218 	val = zx_tdm_readl(tdm, REG_TIMING_CTRL);  in zx_tdm_hw_params()
220 	zx_tdm_writel(tdm, REG_TIMING_CTRL, val);  in zx_tdm_hw_params()
221 	zx_tdm_writel(tdm, REG_TS_MASK0, mask);  in zx_tdm_hw_params()
223 	if (tdm->master)  in zx_tdm_hw_params()
224 		ret = clk_set_rate(tdm->dai_wclk,  in zx_tdm_hw_params()
322 static void zx_tdm_init_state(struct zx_tdm_info *tdm)  in zx_tdm_init_state()  argument
326 	zx_tdm_writel(tdm, REG_PROCESS_CTRL, PROCESS_DISABLE_ALL);  in zx_tdm_init_state()
328 	val = zx_tdm_readl(tdm, REG_TIMING_CTRL);  in zx_tdm_init_state()
332 	zx_tdm_writel(tdm, REG_TIMING_CTRL, val);  in zx_tdm_init_state()
334 	zx_tdm_writel(tdm, REG_INT_EN, INT_DISABLE_ALL);  in zx_tdm_init_state()
338 	zx_tdm_writel(tdm, REG_INT_STATUS, INT_STATUS_MASK);  in zx_tdm_init_state()
339 	zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, FIFOCTRL_RX_FIFO_RST);  in zx_tdm_init_state()
340 	zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, FIFOCTRL_TX_FIFO_RST);  in zx_tdm_init_state()
342 	val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);  in zx_tdm_init_state()
345 	zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);  in zx_tdm_init_state()
347 	val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);  in zx_tdm_init_state()
350 	zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);  in zx_tdm_init_state()