Lines Matching refs:clk_pll_a
64 clk_disable_unprepare(data->clk_pll_a); in tegra_asoc_utils_set_rate()
66 err = clk_set_rate(data->clk_pll_a, new_baseclock); in tegra_asoc_utils_set_rate()
80 err = clk_prepare_enable(data->clk_pll_a); in tegra_asoc_utils_set_rate()
113 clk_disable_unprepare(data->clk_pll_a); in tegra_asoc_utils_set_ac97_rate()
119 err = clk_set_rate(data->clk_pll_a, pll_rate); in tegra_asoc_utils_set_ac97_rate()
133 err = clk_prepare_enable(data->clk_pll_a); in tegra_asoc_utils_set_ac97_rate()
178 data->clk_pll_a = clk_get(dev, "pll_a"); in tegra_asoc_utils_init()
179 if (IS_ERR(data->clk_pll_a)) { in tegra_asoc_utils_init()
181 ret = PTR_ERR(data->clk_pll_a); in tegra_asoc_utils_init()
210 clk_put(data->clk_pll_a); in tegra_asoc_utils_init()
220 clk_put(data->clk_pll_a); in tegra_asoc_utils_fini()