71 static void bdw_host_done(struct snd_sof_dev *sdev);
72 static void bdw_dsp_done(struct snd_sof_dev *sdev);
73 static void bdw_get_reply(struct snd_sof_dev *sdev);
79 static int bdw_run(struct snd_sof_dev *sdev)  in bdw_run()  argument
82 	snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,  in bdw_run()
87 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,  in bdw_run()
94 static int bdw_reset(struct snd_sof_dev *sdev)  in bdw_reset()  argument
97 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,  in bdw_reset()
105 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,  in bdw_reset()
112 static int bdw_set_dsp_D0(struct snd_sof_dev *sdev)  in bdw_set_dsp_D0()  argument
118 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,  in bdw_set_dsp_D0()
123 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,  in bdw_set_dsp_D0()
127 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS,  in bdw_set_dsp_D0()
132 		reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS)  in bdw_set_dsp_D0()
147 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,  in bdw_set_dsp_D0()
152 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  in bdw_set_dsp_D0()
159 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,  in bdw_set_dsp_D0()
168 	bdw_reset(sdev);  in bdw_set_dsp_D0()
171 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,  in bdw_set_dsp_D0()
180 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,  in bdw_set_dsp_D0()
188 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,  in bdw_set_dsp_D0()
192 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  SHIM_CSR2,  in bdw_set_dsp_D0()
197 	snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,  in bdw_set_dsp_D0()
204 	snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,  in bdw_set_dsp_D0()
206 	snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,  in bdw_set_dsp_D0()
211 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);  in bdw_set_dsp_D0()
212 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);  in bdw_set_dsp_D0()
213 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);  in bdw_set_dsp_D0()
214 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);  in bdw_set_dsp_D0()
219 static void bdw_get_registers(struct snd_sof_dev *sdev,  in bdw_get_registers()  argument
224 	u32 offset = sdev->dsp_oops_offset;  in bdw_get_registers()
227 	sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));  in bdw_get_registers()
233 		dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",  in bdw_get_registers()
238 	sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));  in bdw_get_registers()
242 	sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));  in bdw_get_registers()
245 static void bdw_dump(struct snd_sof_dev *sdev, u32 flags)  in bdw_dump()  argument
253 	status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);  in bdw_dump()
254 	panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);  in bdw_dump()
255 	bdw_get_registers(sdev, &xoops, &panic_info, stack,  in bdw_dump()
257 	snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,  in bdw_dump()
267 	struct snd_sof_dev *sdev = context;  in bdw_irq_handler()  local
272 	isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);  in bdw_irq_handler()
281 	struct snd_sof_dev *sdev = context;  in bdw_irq_thread()  local
284 	imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);  in bdw_irq_thread()
285 	ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);  in bdw_irq_thread()
291 		snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  in bdw_irq_thread()
295 		spin_lock_irq(&sdev->ipc_lock);  in bdw_irq_thread()
304 		bdw_get_reply(sdev);  in bdw_irq_thread()
305 		snd_sof_ipc_reply(sdev, ipcx);  in bdw_irq_thread()
307 		bdw_dsp_done(sdev);  in bdw_irq_thread()
309 		spin_unlock_irq(&sdev->ipc_lock);  in bdw_irq_thread()
312 	ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);  in bdw_irq_thread()
318 		snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  in bdw_irq_thread()
324 			snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) +  in bdw_irq_thread()
327 			snd_sof_ipc_msgs_rx(sdev);  in bdw_irq_thread()
330 		bdw_host_done(sdev);  in bdw_irq_thread()
340 static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)  in bdw_send_msg()  argument
343 	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,  in bdw_send_msg()
345 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);  in bdw_send_msg()
350 static void bdw_get_reply(struct snd_sof_dev *sdev)  in bdw_get_reply()  argument
352 	struct snd_sof_ipc_msg *msg = sdev->msg;  in bdw_get_reply()
362 		dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");  in bdw_get_reply()
367 	sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));  in bdw_get_reply()
375 			dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",  in bdw_get_reply()
382 			sof_mailbox_read(sdev, sdev->host_box.offset,  in bdw_get_reply()
389 static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev)  in bdw_get_mailbox_offset()  argument
394 static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id)  in bdw_get_window_offset()  argument
399 static void bdw_host_done(struct snd_sof_dev *sdev)  in bdw_host_done()  argument
402 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,  in bdw_host_done()
407 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,  in bdw_host_done()
411 static void bdw_dsp_done(struct snd_sof_dev *sdev)  in bdw_dsp_done()  argument
414 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,  in bdw_dsp_done()
418 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,  in bdw_dsp_done()
425 static int bdw_probe(struct snd_sof_dev *sdev)  in bdw_probe()  argument
427 	struct snd_sof_pdata *pdata = sdev->pdata;  in bdw_probe()
430 		container_of(sdev->dev, struct platform_device, dev);  in bdw_probe()
442 		dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",  in bdw_probe()
447 	dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);  in bdw_probe()
448 	sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);  in bdw_probe()
449 	if (!sdev->bar[BDW_DSP_BAR]) {  in bdw_probe()
450 		dev_err(sdev->dev,  in bdw_probe()
455 	dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);  in bdw_probe()
458 	sdev->mmio_bar = BDW_DSP_BAR;  in bdw_probe()
459 	sdev->mailbox_bar = BDW_DSP_BAR;  in bdw_probe()
460 	sdev->dsp_oops_offset = MBOX_OFFSET;  in bdw_probe()
469 		dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n",  in bdw_probe()
474 	dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);  in bdw_probe()
475 	sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size);  in bdw_probe()
476 	if (!sdev->bar[BDW_PCI_BAR]) {  in bdw_probe()
477 		dev_err(sdev->dev,  in bdw_probe()
482 	dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]);  in bdw_probe()
485 	sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);  in bdw_probe()
486 	if (sdev->ipc_irq < 0)  in bdw_probe()
487 		return sdev->ipc_irq;  in bdw_probe()
489 	dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);  in bdw_probe()
490 	ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,  in bdw_probe()
492 					IRQF_SHARED, "AudioDSP", sdev);  in bdw_probe()
494 		dev_err(sdev->dev, "error: failed to register IRQ %d\n",  in bdw_probe()
495 			sdev->ipc_irq);  in bdw_probe()
500 	ret = bdw_set_dsp_D0(sdev);  in bdw_probe()
502 		dev_err(sdev->dev, "error: failed to set DSP D0\n");  in bdw_probe()
507 	ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));  in bdw_probe()
509 		dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);  in bdw_probe()
514 	snd_sof_dsp_mailbox_init(sdev, MBOX_OFFSET, MBOX_SIZE, 0, 0);  in bdw_probe()