Lines Matching refs:clk_prepare_enable

120 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);  in mt8183_afe_enable_clock()
127 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);  in mt8183_afe_enable_clock()
143 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);  in mt8183_afe_enable_clock()
159 	ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);  in mt8183_afe_enable_clock()
166 	ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]);  in mt8183_afe_enable_clock()
173 	ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]);  in mt8183_afe_enable_clock()
180 	ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]);  in mt8183_afe_enable_clock()
187 	ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]);  in mt8183_afe_enable_clock()
237 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);  in apll1_mux_setting()
253 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);  in apll1_mux_setting()
311 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);  in apll2_mux_setting()
327 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);  in apll2_mux_setting()
387 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);  in mt8183_apll1_enable()
394 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);  in mt8183_apll1_enable()
441 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);  in mt8183_apll2_enable()
448 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);  in mt8183_apll2_enable()
558 		ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);  in mt8183_mck_enable()
575 	ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);  in mt8183_mck_enable()