Lines Matching full:14
217 #define RT5670_VOL_L_MUTE (0x1 << 14)
218 #define RT5670_VOL_L_SFT 14
315 #define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14)
316 #define RT5670_STO1_ADC_L_BST_SFT 14
333 #define RT5670_M_ADC_L1 (0x1 << 14)
334 #define RT5670_M_ADC_L1_SFT 14
355 #define RT5670_M_MONO_ADC_L1 (0x1 << 14)
356 #define RT5670_M_MONO_ADC_L1_SFT 14
385 #define RT5670_M_DAC1_L (0x1 << 14)
386 #define RT5670_M_DAC1_L_SFT 14
405 #define RT5670_M_DAC_L1 (0x1 << 14)
406 #define RT5670_M_DAC_L1_SFT 14
431 #define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
432 #define RT5670_M_DAC_L1_MONO_L_SFT 14
459 #define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
460 #define RT5670_STO_L_DAC_L_VOL_SFT 14
525 #define RT5670_M_PDM1_L (0x1 << 14)
526 #define RT5670_M_PDM1_L_SFT 14
592 #define RT5670_M_HPVOL_HM (0x1 << 14)
593 #define RT5670_M_HPVOL_HM_SFT 14
610 #define RT5670_M_DAC_L2_MA (0x1 << 14)
611 #define RT5670_M_DAC_L2_MA_SFT 14
688 #define RT5670_M_DAC_R1_LM (0x1 << 14)
689 #define RT5670_M_DAC_R1_LM_SFT 14
700 #define RT5670_PWR_I2S2 (0x1 << 14)
701 #define RT5670_PWR_I2S2_BIT 14
720 #define RT5670_PWR_ADC_MF_L (0x1 << 14)
721 #define RT5670_PWR_ADC_MF_L_BIT 14
742 #define RT5670_PWR_FV1 (0x1 << 14)
743 #define RT5670_PWR_FV1_BIT 14
786 #define RT5670_PWR_OM_R (0x1 << 14)
787 #define RT5670_PWR_OM_R_BIT 14
902 #define RT5670_DAC_L_OSR_MASK (0x3 << 14)
903 #define RT5670_DAC_L_OSR_SFT 14
904 #define RT5670_DAC_L_OSR_128 (0x0 << 14)
905 #define RT5670_DAC_L_OSR_64 (0x1 << 14)
906 #define RT5670_DAC_L_OSR_32 (0x2 << 14)
907 #define RT5670_DAC_L_OSR_16 (0x3 << 14)
924 #define RT5670_DMIC_2_EN_MASK (0x1 << 14)
925 #define RT5670_DMIC_2_EN_SFT 14
926 #define RT5670_DMIC_2_DIS (0x0 << 14)
927 #define RT5670_DMIC_2_EN (0x1 << 14)
968 #define RT5670_SCLK_SRC_MASK (0x3 << 14)
969 #define RT5670_SCLK_SRC_SFT 14
970 #define RT5670_SCLK_SRC_MCLK (0x0 << 14)
971 #define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
972 #define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
1006 #define RT5670_M1_T_MASK (0x1 << 14)
1007 #define RT5670_M1_T_SFT 14
1008 #define RT5670_M1_T_I2S2 (0x0 << 14)
1009 #define RT5670_M1_T_I2S2_D3 (0x1 << 14)
1217 #define RT5670_SPK_AG_MASK (0x1 << 14)
1218 #define RT5670_SPK_AG_SFT 14
1219 #define RT5670_SPK_AG_DIS (0x0 << 14)
1220 #define RT5670_SPK_AG_EN (0x1 << 14)
1227 #define RT5670_MIC2_BS_MASK (0x1 << 14)
1228 #define RT5670_MIC2_BS_SFT 14
1229 #define RT5670_MIC2_BS_9AV (0x0 << 14)
1230 #define RT5670_MIC2_BS_75AV (0x1 << 14)
1281 #define RT5670_EQ_UPD (0x1 << 14)
1282 #define RT5670_EQ_UPD_BIT 14
1344 #define RT5670_DRC_AGC_MASK (0x1 << 14)
1345 #define RT5670_DRC_AGC_SFT 14
1346 #define RT5670_DRC_AGC_DIS (0x0 << 14)
1347 #define RT5670_DRC_AGC_EN (0x1 << 14)
1459 #define RT5670_IRQ_OT_MASK (0x1 << 14)
1460 #define RT5670_IRQ_OT_SFT 14
1461 #define RT5670_IRQ_OT_BP (0x0 << 14)
1462 #define RT5670_IRQ_OT_NOR (0x1 << 14)
1489 #define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
1490 #define RT5670_IRQ_MB2_OC_SFT 14
1491 #define RT5670_IRQ_MB2_OC_BP (0x0 << 14)
1492 #define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
1519 #define RT5670_GP2_PIN_MASK (0x1 << 14)
1520 #define RT5670_GP2_PIN_SFT 14
1521 #define RT5670_GP2_PIN_GPIO2 (0x0 << 14)
1522 #define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
1630 #define RT5670_SCB_MASK (0x1 << 14)
1631 #define RT5670_SCB_SFT 14
1632 #define RT5670_SCB_DIS (0x0 << 14)
1633 #define RT5670_SCB_EN (0x1 << 14)
1660 #define RT5670_M_MP3_R_MASK (0x1 << 14)
1661 #define RT5670_M_MP3_R_SFT 14
1692 #define RT5670_3D_HP_MASK (0x1 << 14)
1693 #define RT5670_3D_HP_SFT 14
1694 #define RT5670_3D_HP_DIS (0x0 << 14)
1695 #define RT5670_3D_HP_EN (0x1 << 14)
1779 #define RT5670_SPO_SV_MASK (0x1 << 14)
1780 #define RT5670_SPO_SV_SFT 14
1781 #define RT5670_SPO_SV_DIS (0x0 << 14)
1782 #define RT5670_SPO_SV_EN (0x1 << 14)
1872 #define RT5670_DP_ATT_MASK (0x3 << 14)
1873 #define RT5670_DP_ATT_SFT 14