Lines Matching full:14
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
179 #define RT5651_VOL_L_SFT 14
261 #define RT5651_ADC_L_BST_MASK (0x3 << 14)
262 #define RT5651_ADC_L_BST_SFT 14
269 #define RT5651_M_STO1_ADC_L1 (0x1 << 14)
270 #define RT5651_M_STO1_ADC_L1_SFT 14
287 #define RT5651_M_STO2_ADC_L1 (0x1 << 14)
288 #define RT5651_M_STO2_ADC_L1_SFT 14
315 #define RT5651_M_IF1_DAC_L (0x1 << 14)
316 #define RT5651_M_IF1_DAC_L_SFT 14
323 #define RT5651_M_DAC_L1_MIXL (0x1 << 14)
324 #define RT5651_M_DAC_L1_MIXL_SFT 14
349 #define RT5651_M_STO_DD_L1 (0x1 << 14)
350 #define RT5651_M_STO_DD_L1_SFT 14
377 #define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
378 #define RT5651_STO_L_DAC_L_VOL_SFT 14
397 #define RT5651_TXDP_SRC_MASK (0x1 << 14)
398 #define RT5651_TXDP_SRC_SFT 14
399 #define RT5651_TXDP_SRC_NOR (0x0 << 14)
400 #define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
403 #define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
404 #define RT5651_DAC_L2_SEL_SFT 14
405 #define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
406 #define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
407 #define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
408 #define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
470 #define RT5651_M_PDM_L (0x1 << 14)
471 #define RT5651_M_PDM_L_SFT 14
564 #define RT5651_M_DAC1_HM (0x1 << 14)
565 #define RT5651_M_DAC1_HM_SFT 14
572 #define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
573 #define RT5651_G_RM_L_SM_L_SFT 14
594 #define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
595 #define RT5651_G_RM_R_SM_R_SFT 14
618 #define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
619 #define RT5651_M_DAC_L1_SPM_L_SFT 14
642 #define RT5651_M_DAC_L2_MM (0x1 << 14)
643 #define RT5651_M_DAC_L2_MM_SFT 14
716 #define RT5651_M_DAC_R1_LM (0x1 << 14)
717 #define RT5651_M_DAC_R1_LM_SFT 14
728 #define RT5651_PWR_I2S2 (0x1 << 14)
729 #define RT5651_PWR_I2S2_BIT 14
742 #define RT5651_PWR_ADC_STO2_F (0x1 << 14)
743 #define RT5651_PWR_ADC_STO2_F_BIT 14
754 #define RT5651_PWR_FV1 (0x1 << 14)
755 #define RT5651_PWR_FV1_BIT 14
783 #define RT5651_PWR_BST2 (0x1 << 14)
784 #define RT5651_PWR_BST2_BIT 14
807 #define RT5651_PWR_OM_R (0x1 << 14)
808 #define RT5651_PWR_OM_R_BIT 14
934 #define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
935 #define RT5651_TDM_MODE_SEL_SFT 14
936 #define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
937 #define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
988 #define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
989 #define RT5651_TDM_CH_VAL_SEL_SFT 14
990 #define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
991 #define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
1062 #define RT5651_SCLK_SRC_MASK (0x3 << 14)
1063 #define RT5651_SCLK_SRC_SFT 14
1064 #define RT5651_SCLK_SRC_MCLK (0x0 << 14)
1065 #define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1066 #define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
1115 #define RT5651_STO2_ASRC_EN (0x1 << 14)
1116 #define RT5651_STO2_ASRC_EN_SFT 14
1364 #define RT5651_EQ_UPD (0x1 << 14)
1365 #define RT5651_EQ_UPD_BIT 14
1443 #define RT5651_ALC_MASK (0x1 << 14)
1444 #define RT5651_ALC_SFT 14
1445 #define RT5651_ALC_DIS (0x0 << 14)
1446 #define RT5651_ALC_EN (0x1 << 14)
1606 #define RT5651_STA_JD2 (0x1 << 14)
1607 #define RT5651_STA_JD2_BIT 14
1634 #define RT5651_GP2_PIN_MASK (0x1 << 14)
1635 #define RT5651_GP2_PIN_SFT 14
1636 #define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
1637 #define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1668 #define RT5651_GP5_DR_MASK (0x1 << 14)
1669 #define RT5651_GP5_DR_SFT 14
1670 #define RT5651_GP5_DR_IN (0x0 << 14)
1671 #define RT5651_GP5_DR_OUT (0x1 << 14)
1772 #define RT5651_SCB_MASK (0x1 << 14)
1773 #define RT5651_SCB_SFT 14
1774 #define RT5651_SCB_DIS (0x0 << 14)
1775 #define RT5651_SCB_EN (0x1 << 14)
1802 #define RT5651_M_MP3_R_MASK (0x1 << 14)
1803 #define RT5651_M_MP3_R_SFT 14
1834 #define RT5651_3D_HP_MASK (0x1 << 14)
1835 #define RT5651_3D_HP_SFT 14
1836 #define RT5651_3D_HP_DIS (0x0 << 14)
1837 #define RT5651_3D_HP_EN (0x1 << 14)
2026 #define RT5651_DP_ATT_MASK (0x3 << 14)
2027 #define RT5651_DP_ATT_SFT 14