83 #define CM_REG_FUNCTRL1		0x04  macro
831 	val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);  in snd_cmipci_pcm_prepare()
839 	snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);  in snd_cmipci_pcm_prepare()
1254 			snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in setup_spdif_playback()
1270 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in setup_spdif_playback()
1338 		val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);  in snd_cmipci_silence_hack()
1341 		snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);  in snd_cmipci_silence_hack()
1397 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);  in snd_cmipci_capture_spdif_prepare()
1419 	snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);  in snd_cmipci_capture_spdif_hw_free()
2424 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2425 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2430 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2436 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2488 				snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in snd_cmipci_spdout_enable_put()
2491 				snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in snd_cmipci_spdout_enable_put()
2887 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_create_gameport()
2902 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_free_gameport()
2920 		snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);  in snd_cmipci_free()
3085 	snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);  in snd_cmipci_create()
3099 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);  in snd_cmipci_create()
3173 			snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);  in snd_cmipci_create()
3178 				snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,  in snd_cmipci_create()
3237 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_create()
3312 	CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,