Lines Matching defs:drm_amdgpu_info_device
926 struct drm_amdgpu_info_device { struct
928 __u32 device_id;
930 __u32 chip_rev;
931 __u32 external_rev;
933 __u32 pci_rev;
934 __u32 family;
935 __u32 num_shader_engines;
936 __u32 num_shader_arrays_per_engine;
938 __u32 gpu_counter_freq;
939 __u64 max_engine_clock;
940 __u64 max_memory_clock;
942 __u32 cu_active_number;
944 __u32 cu_ao_mask;
945 __u32 cu_bitmap[4][4];
947 __u32 enabled_rb_pipes_mask;
948 __u32 num_rb_pipes;
949 __u32 num_hw_gfx_contexts;
950 __u32 _pad;
951 __u64 ids_flags;
953 __u64 virtual_address_offset;
955 __u64 virtual_address_max;
957 __u32 virtual_address_alignment;
959 __u32 pte_fragment_size;
960 __u32 gart_page_size;
962 __u32 ce_ram_size;
964 __u32 vram_type;
966 __u32 vram_bit_width;
968 __u32 vce_harvest_config;
970 __u32 gc_double_offchip_lds_buf;
972 __u64 prim_buf_gpu_addr;
974 __u64 pos_buf_gpu_addr;
976 __u64 cntl_sb_buf_gpu_addr;
978 __u64 param_buf_gpu_addr;
979 __u32 prim_buf_size;
980 __u32 pos_buf_size;
981 __u32 cntl_sb_buf_size;
982 __u32 param_buf_size;
984 __u32 wave_front_size;
986 __u32 num_shader_visible_vgprs;
988 __u32 num_cu_per_sh;
990 __u32 num_tcc_blocks;
992 __u32 gs_vgt_table_depth;
994 __u32 gs_prim_buffer_depth;
996 __u32 max_gs_waves_per_vgt;
997 __u32 _pad1;
999 __u32 cu_ao_bitmap[4][4];
1001 __u64 high_va_offset;
1003 __u64 high_va_max;
1005 __u32 pa_sc_tile_steering_override;
1007 __u64 tcc_disabled_mask;