Lines Matching full:supported

24 /* SDW Master Device Number, not supported yet */
178  * @SDW_DPN_FULL: Full Data Port is supported
209  * @num_words: number of wordlengths supported
210  * @words: wordlengths supported
235  * @bus_num_freq: Number of discrete frequencies supported
239  * @num_freq: Number of discrete sampling frequency supported
245  * changed to a frequency supported by this mode or compatible modes
270  * @num_words: Number of discrete supported wordlengths
271  * @words: Discrete supported wordlength
280  * @max_ch: Maximum channels supported
281  * @min_ch: Minimum channels supported
282  * @num_ch: Number of discrete channels supported
283  * @ch: Discrete channels supported
284  * @num_ch_combinations: Number of channel combinations supported
285  * @ch_combinations: Channel combinations supported
286  * @modes: SDW mode supported
289  * @block_pack_mode: Type of block port mode supported
290  * @port_encoding: Payload Channel Sample encoding schemes supported
291  * @audio_modes: Audio modes supported
320  * @wake_capable: Wake-up events are supported
321  * @test_mode_capable: If test mode is supported
322  * @clk_stop_mode1: Clock-Stop Mode 1 is supported
323  * @simple_clk_stop_capable: Simple clock mode is supported
370  * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
372  * @num_clk_gears: Number of clock gears supported
373  * @clk_gears: Clock gears supported
374  * @num_clk_freq: Number of clock frequencies supported, in Hz
375  * @clk_freq: Clock frequencies supported, in Hz
379  * @dynamic_frame: Dynamic frame shape supported
500  * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
625  * data lane is supported in bus
744  * are supported. This flag is populated by drivers after reading